ATE Guards IC Quality
Despite inroads from DFT and BIST techniques, semiconductor production-test systems remain the ultimate guarantors of chip reliability.
Rick Nelson, Senior Technical Editor -- Test & Measurement World, 6/1/2000
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For more information: • A version of this article appeared in the October-November 2000 issue of Test & Measurement Europe. |
There’s just one problem—despite the increasing capabilities of DFT and BIST techniques, and despite the quality levels achieved by silicon foundries, production ATE remains the king of chip quality assurance and will remain an important part of the production process. King ATE will benefit from the support of the dukes of DFT, the bishops of BIST, and the knights of Known Good Die. But those underlings play no more than a supporting role in bringing high-quality devices to market on time.
That’s not to belittle the supporting role that the new characters play, whose importance I emphasized last September.1 The Magna Charta has been signed. King ATE’s power is no longer absolute. But in the uneasy peace that ensues between ATE loyalists and the opposing Roundheads, ATE remains well armed:
• Until BIST can embed high-wattage power supplies and a start button in silicon, IC test will require a production-floor work cell to provide power and generate patterns that initiate the activities of any onboard self-test features. The tester footprint is not going to vanish from the production floor.
• Of course, you don’t need to spend upwards of $2,000 per pin to power up a chip and generate some patterns that initiate self-test. You may, however, find such an expenditure more palatable than burdening your silicon real estate with extensive BIST circuitry or DFT access roads. The price of silicon overhead turning a one-chip product into a two-chip one would be formidable indeed.
• BIST can isolate and test macro cells and other components within complex chips, but it doesn’t do a good job of indicating how well those components will work together. An ATE system applying inputs and measuring outputs remains the best way to functionally test an IC.
• Chip-vendor executives who honestly believe their semiconductor processes are so good that device-test ATE has become irrelevant may pose a threat to ATE, but the risks of failure to test are so catastrophic2 that it’s hard to take the threat seriously.
Controlling Cost of Test
Nevertheless, ATE vendors recognize that they face pressure to deliver cost-effective solutions. Pat Gelsinger, a vice president at Intel’s Microprocessor Products Group (Santa Clara, CA), was adamant on that point when he addressed the International Test Conference last fall.3 The cost to manufacture a transistor has fallen dramatically, from about a tenth of a cent in 1983 to less than a thousandth of a cent today. The cost of testing each transistor, however, has remained flat, near 10-5 cents. This situation, Gelsinger told the ITC, is intolerable: “We must find radical departures that allow us to continue to drive down the test cost per manufactured transistor.”
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| Figure 1. An oscilloscope eye diagram can help you measure an ATE system’s overall pin-to-pin timing accuracy. Here, Dt, between the vertical cursor lines, is 140 ps, indicating an OTA of w 70 ps. (Courtesy of Schlumberger.) |
Gelsinger is a DFT and BIST partisan, having worked on DFT for the ’286 and ’386 processors. In addition to its flat cost-per-transistor trends, he indicts ATE for failure to improve sufficiently in performance. In 1985, he says, he used an ATE system with 1-ns edge-placement accuracy to test an 8-MHz ’286. Today, he must make due with 100-ps edge-placement accuracies—a tenfold improvement—to test Pentium III chips operating at 100 times the speed of their 1985 predecessors.
ATE vendors are aware of the challenges and are striving to make adjustments (see the product survey chart, or download this article and chart as a pdf). Recognizing the effect of edge-placement accuracy on test yields,4 vendors are improving overall timing accuracies (Fig. 1). They also are developing novel ways to provide mixed-signal stimuli to UUTs and to carry mixed-signal responses to instrumentation (Fig. 2). Tester-per-pin architectures are ensuring high accuracies while maintaining high production throughput. Furthermore, vendors are optimizing their systems for the gamut of devices, developing testers focusing on a range of components from relatively low-speed flash-memory and microcontroller products to high-speed RFICs (Fig. 3).
What’s more, ATE vendors are providing the temperature-control mechanisms that keep high-powered chips from overheating during the test process. They are providing techniques such as differential drive and measurement functions to ensure signal integrity at high speeds while eliminating the accumulation of timing errors that could normally accompany a differential instrument configuration. And they are fitting more and more circuitry on their systems’ test heads, bringing test hardware closer to the device under test. And they offer one feature that BIST can never mimic—they can provide gigabit-per-pin depths of scan memory for fault diagnostic and analysis operations.
Intel’s Gelsinger envisions a future in which full-featured ATE serves a curtailed role in validating early a)
silicon and providing correlation and validation of test steps integrated throughout the manufacturing process. Production device testers, he says, will have far fewer channels than today’s as BIST circuitry takes over the test tasks that currently require individual pin drivers.
Figure 2. Mixed-signal testing can require a double-barreled attack. Here, mixed-signal Pogo pins mounted on a system configuration module complement digital Pogo pins on the test head. (Courtesy of LTX.)
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Figure 3. (a) A VXIbus-based RFIC tester relies on RF pin drivers at the test head. (b) The drivers down-convert reference and test signals close to the DUT. Dual digitizers process forward and reverse signals simultaneously, making IF signals available for S-parameter measurements. (Courtesy of Agilent Technologies.)
Gelsinger has been wrong before, though. He admits to predicting in 1987 that by the year 2000 you would be able to buy a 250-MHz microprocessor from his company. (Of course, you can’t—Intel no longer sells processors rated less than 433 MHz.) BIST and DFT will play big roles in testing the parts of tomorrow’s chips that are inaccessible to an external tester. But if Gelsinger underestimates those chips’ complexities as he did processor speeds circa 2000, there will be plenty of chores for full-featured, mixed-signal device-test ATE to do. T&MW
REFERENCES
1. Nelson, Rick, “Design Techniques Ensure Testable SOCs,” Test & Measurement World, September 1999. p. 32.
2. Strassberg, Dan, “BIST and ATE team to tame IC-test cost,” EDN, March 2, 2000. p. 93.
3. The address is reprinted in “Discontinuities Driven by a Billion Connected Machines,” IEEE Design & Test of Computers, January–March 2000. pp. 7–15, computer.org/dt/dt2000/pdf/d1007.pdf.
4. Mack, Chris, and Wajih Dalal, “RDRAMs Benefit from High-Speed Testers,” Test & Measurement World, November 1999. pp. 15–16.
You can contact Rick Nelson at rnelson@tmworld.com
