Add Logic Gear to Analog Test
Combining an analog test system with a VXI data generator/analyzer creates a low-cost, mixed-signal test system.
Richard Techmanski, Linear Technology, Milpitas, CA -- Test & Measurement World, 9/1/2000
Many previously all-analog IC designs are benefiting from the addition of digital intelligence in the form of state machines and other simple logic circuits. One example is our company’s smart battery-charger IC, which we created by adding digital logic to one of our conventional battery-charger products. Adding digital capabilities to an analog part, however, forced our test department to acquire mixed-signal test capability.
We already had a large installed base of LTX (Westwood, MA) analog test systems and a large investment in programs to test the analog blocks included in the new mixed-signal product. So, instead of investing millions of dollars in new mixed-signal ATE systems and starting from ground zero to develop new test programs, we combined our existing analog test platform with a relatively inexpensive VXIbus data generator/
analyzer (DGA). We chose the Agilent Technologies (Palo Alto, CA) Model 81200; other open-bus-based instruments or combination of instruments would work as well. We also acquired software that would help us develop the necessary digital test vectors from simulation.
Our LTC17591 smart battery charger is an integrated circuit designed to be part of a smart-battery charging system based on the System Management Bus (SMBus) specification, originally conceived by Intel. SMBus is a two-wire serial interface, consisting of clock and data, through which simple power-related chips can communicate with the rest of the system they serve. SMBus smart battery-charger ICs connect to the battery through a five-terminal connection: the two conventional-battery terminals, a terminal (referenced to the negative battery terminal) that accommodates a thermistor output, and two terminals that connect to the SMBus communication link.
We created our smart battery charger by adding these digital blocks to a conventional battery charger: an SMBus controller, a thermistor decoder, a charger controller, and multiple 16-bit registers. The registers indicate device status and enable a host to program the part for specific charging currents and voltages.
The Test Equipment
Figure 1 shows a block diagram of the mixed-signal test system we devised to test the smart battery-charger IC. The DGA and analog tester communicate with each other over an IEEE 488 link—the only direct link between the analog and digital portions of the system. The DGA sends digital stimuli to and receives digital responses from the test-bench circuitry, which is a custom-built circuit board carrying the DUT socket and associated mixed-signal interface circuitry. Similarly, the analog tester provides analog stimulus signals to and receives analog response signals from the test bench, which connects these signals to the DUT.
The analog and digital portions of this system aren’t synchronized; they exchange handshaking signals only. The analog tester initializes the test procedure by telling (over the IEEE 488 link) the Slot-0 controller to load the appropriate settings stored on the DGA hard drive. These settings include DUT-specific DGA hardware-configuration information such as system clock period, generator drive levels required by the DUT, analyzer compare thresholds, and test vectors.
In what we call the “immediate” operational mode (which the host establishes over the IEEE 488 link), the DGA in real time applies a test vector and compares the captured result to the expected data. The DGA steps through the vectors, as defined in the pattern sequence, and stops at a user-specified location or after all vectors have been applied. After waiting a sufficient execution time (the number of vectors times the system clock period), the analog tester can query the DGA to determine how many (if any) functional bit errors occurred. This mode serves for functional testing of the DUT.
One aspect of operation in this immediate mode is that when the DGA we used stops, its outputs return to zero. Although not an issue for functional testing, this DGA characteristic presents a problem for parametric tests. Most mixed-signal and digital ICs require some form of setup, through functional preconditioning, to enable the measurement of parametric specifications. Removing the stimulus from the DUT would remove the necessary setup condition and, most likely, place the DUT in an improper state for the parametric measurement.
Figure 1. The low-cost mixed-signal test system consists of an inexpensive analog tester and a data generator/analyzer interfacing to the DUT through a mixed-signal test-bench circuit board.
For example, when testing the threshold of our smart battery charger IC’s DCDIV pin (used to detect the presence of an external power source), the charge-enable pin (CHGEN) monitors the DCDIV comparator threshold. First, we must condition the DUT, through functional setup, to enable charger operation. Then, the analog tester can ramp the DCDIV pin voltage up and down, while observing the logic state of the CHGEN pin, to measure the upper and lower threshold. The tester could not measure these thresholds if the DGA outputs returned to zero, because the DUT inputs required to establish charger operation would not be in the correct state.
To get around this issue, we programmed the DGA to run in its “gated” operational mode. In this mode, as long as the DGA’s EXT input is low, the DGA system clock runs. Driving EXT high “gates-off” the DGA system clock, which preserves both the DGA vector-pointer position and the current output levels. Driving the DGA EXT input back low allows it to continue vector execution. We achieve gated control by feeding one of the DGA output channels back to the EXT input. We keep this input low until the DGA reaches a point in the vector sequence where it is ready for the analog tester to do something. At that point, the DGA output channel drives the EXT input high and freezes the DGA in its current state.
The analog tester can sense the DGA’s EXT input going high and knows that it is time to perform the next step in its test program. When the tester finishes its part, it drives the DGA gate low momentarily, and the DGA proceeds to the next vector location. Handshaking procedures through the test bench and IEEE 488 link let us integrate these quite different pieces of test equipment into a single, well-coordinated mixed-signal test system. Handshaking allows the very fast digital test equipment to coordinate with the much slower analog tester.
One especially useful facet of our test bench is that it lets us test analog DUT functions with the digital tester. For example, we can simulate the analog resistance value from a smart battery’s thermistor using the decoder circuit shown in Figure 2. The decoder presents eight resistances to the two thermistor input pins to represent thermistor values below and above thresholds. We chose this approach because our legacy analog testers don’t provide programmable resistors. This method allows switching resistors in and out in real time.
Figure 2. The test bench uses a 3-into-8 decoder and eight physical resistors to verify that the DUT responds properly to different thermistor values.
Figure 3. The test-vector generation procedure begins with a Verilog simulation and ends with the creation of digital test patterns ready for use by the DGA.
Test Vector Generation
Figure 3 illustrates the process for creating the test vectors necessary to run the digital portion of the test. We used a Verilog logic-simulation/verification tool to develop the test vectors needed to run on the DGA. We set up the simulation environment, which provides stimulus to a model of the DUT, to duplicate the test-bench circuitry—this duplication guarantees maximum fault coverage.
Once we had simulated the test bench and DUT, we let the simulator produce a test-bench output—a response vector—for each DGA output pattern. The vector set that the simulation produced became a signature of a good DUT plugged into the actual test bench.
To make the conversion from simulator output to DGA test vectors, we began with TDS software from Fluence Technology (Beaverton, OR). This software conditions simulator results to fit the capabilities of off-the-shelf digital test systems. In our case, it moved the data-pulse edges to coincide with the DGA’s clock period. Generally, TDS converts the simulator output to its own format and then uses an out-converter to format the data for a target digital test system.
Because our test system is not a standard production-test system, TDS doesn’t have a specific out-converter for it. But TDS does have a generic out-converter that produces an ASCII file. To convert that file to the cyclized data that the DGA requires, we wrote a Perl script that fills in all the blanks and reformats the ASCII file for the DGA. The Perl script also adds some header and footer information to the file as required by the DGA. This Perl script’s output is then a test-vector file ready to import into the DGA.
Real-Time Mixed-Signal Testing
Armed with digital test vectors loaded into the DGA and the analog test procedures we used for the original all-analog circuit, we were ready to test the mixed-signal IC in a production environment. The whole project cost approximately $70,000, which includes the TDS software and the Agilent 81200 populated with 14 NRZ generator channels, one RZ generator channel, and four analyzer channels. The system is expandable: To add more channels to the VXIbus-based DGA, all we have to do is plug more cards into the mainframe.
Because the DGA was originally targeted as a development test tool, integrating the DGA into a mixed-signal production test environment requires some specific customization. We were the first US customer to use it in this application, and since we began the project, Agilent has enhanced the DGA for easier integration. T&MW
FOOTNOTE
1. “LTC1759 Smart Battery Charger,” Datasheet, Linear Technology Corp., Milpitas, CA, www.linear.com/pdf/1759f.pdf.
Richard S. Techmanski is a staff engineer in the Power Products Division of Linear Technology Corp. His work involves developing hardware and software to facilitate new product market introductions. He has a B.S. degree in electrical engineering from Union College in Schenectady, NY.
