Hot Tests Whip Chips into Shape

Test functions migrate toward burn-in, while thermal control becomes a hot topic at final test.

Rick Nelson, Senior Technical Editor -- Test & Measurement World, 10/1/2000

In September 1999, Pat Gelsinger, a vice president and general manager at Intel, called the combination of test and burn-in a “new paradigm.”¹ Gelsinger was a little late with his proclamation—by the time he made his remarks, manufacturers had already been offering test-and-burn-in systems for several months.² The plaudits awarded to this “new paradigm” by large independent device manufacturers (IDMs) like Intel, however, suggests a growing market for such equipment.

Don’t expect a burn-in-with-test system to subsume the role of functional device ATE, though. Burn-in systems, designed to test hundreds of units in parallel over a period of many hours, typically offer speeds in the tens of megahertz range. In contrast, ATE systems spend a few seconds performing gigahertz-rate tests on from one to 64 devices in parallel. You can, however, expect more ATE-like functions to be performed at the burn-in stage as DUTs acquire more built-in-self-test (BIST) features, beginning with the IEEE 1149 boundary-scan Test Access Port (TAP) connected to internal test structures.

A low-speed intelligent burn-in system with BIST support can provide the DUT input vectors that initiate an on-chip full-speed structural-test sequence, and the system can monitor the resulting DUT output signatures, comparing them with known-good values. Such an approach can free full-speed ATE to perform critical at-speed functional tests on devices that have passed the combined burn-in and full-speed structural-test stage. Whether ATE is successfully offloaded by burn-in test systems will depend on whether structural test proves to be an effective alternative to extensive final functional test—a point that’s hotly debated.³

Basic Burn-in
Burn-in differs from final test in many aspects, beginning with the type of socket used for device test. For a basic burn-in system, you would select burn-in sockets (such as ones depicted on the left) from a firm like Aehr Test Systems, Loranger International, Texas Instruments, Wells-CTI, or Yamaichi Electronics to populate a burn-in board (BIB). You’ll need a socket that’s compatible with your DUT package—or lack of package, if you’re burning-in flip-chip or chip-scale devices that will subsequently be packaged in a RIMM or multichip module, for example.

Each burn-in board might accommodate 50 or more sockets, and a burn-in system, in turn, might hold 32 burn-in boards. In traditional burn-in, called static burn-in, DUTs are loaded into the BIBs’ sockets, the BIBs are placed in the burn-in system’s oven, and the system applies power to the devices and heats them to 125 to 150°C for a period ranging from 12 to 24 hrs. The heating mechanism can be as simple as a convection scheme involving the forced flow of constant-temperature air over burn-in boards, or as complex as having individual heat exchangers independently control the temperature of individual DUTs through conduction.

To develop a successful burn-in strategy, you need detailed knowledge about temperature distributions across a DUT package, across a BIB, and throughout the burn-in oven. Figure 1 illustrates an investigation at the burn-in-socket level for convection control of burn-in temperature. Shown in Figure 1a is a model—developed in Fluent’s IcePak object-based thermal-management software tool—of a two-part heat sink attached to a die. The indicated temperature profile would result from airflow in the positive z-axis direction (upper right rear to lower left front).

Such a model must take into account several variables—including thermal resistances such as semiconductor-junction to package, package to heat sink, and heat sink to air. Ideally, designers want to eliminate the need for a heat-conducting compound to join the DUT and heat sink. Such compounds, suitable for permanent device/heat-sink interfaces, are cumbersome to use during the burn-in process, in which any compound must be cleaned from the DUT and heat sink after the burn-in process completes. Texas Instruments engineers have found thermal compounds generally unnecessary for burning-in DUTs in ceramic packages. Chip-scale devices on organic substrates can be more challenging, they say, and may require some form of heat-transfer compound.

The ultimate test of the accuracy of a finite-analysis model is to evaluate a prototype socket/ DUT/heat-sink combination. In Figure 1b, a hardware prototype develops a similar temperature distribution to that of the Figure 1a model when subjected to a left-to-right airflow in a wind tunnel, shown in Figure 1c. Additional finite-element analysis can predict temperatures across burn-in boards mounted within ovens.

Dynamic burn-in mimics the static burn-in process but also stimulates the DUT’s address, data, and clock inputs at a maximum rate determined by the burn-in system’s electronics. Neither static nor dynamic burn-in monitors DUT responses; parts destroyed by the burn-in process aren’t detected until a subsequent functional-test stage.⁴ Furthermore, the relatively low speeds of dynamic burn-in systems permit them to exercise only the slowest parts at rated speeds, unless higher speed parts include on-chip clocks and BIST circuitry that can exercise the devices during the dynamic burn-in process.

Intelligent Burn-in
Beyond static and dynamic burn-in is the so-called monitored, or intelligent, burn-in. Intelligent burn-in systems not only apply power and signals to DUTs, they also monitor DUT outputs. Therefore, they can guarantee that devices undergoing burn-in are indeed powered up and that input test vectors are being applied. In addition, they can perform some test functions.

Intelligent burn-in systems such as the Model ABES-V from Micro Control Co. include bidirectional pin electronics that resemble that of functional ATE systems (Fig. 2). Despite the architectural similarities, the systems differ significantly. In addition to the aforementioned speed differences, an intelligent burn-in system tests many devices with just a few pins per device—the ABES-V, for example, can test only 256 I/O points per burn-in board; top-of-the-line ATE can test up to 1024 pins per individual device (in single-stage tests). The relatively low pin count per device of burn-in/test systems is compensated for by the fact that DUTs remain in the system for hours rather than seconds, permitting time for sequential tests of the many DUTs in the system. 

Figure 2. Intelligent burn-in systems sport architectures similar to those of functional ATE systems. The Model ABES-V (for Automated Burn-in/Environmental System) from Micro Control Co. can exercise and monitor up to 256 I/O pins per BIB and has a 4-M vector memory depth.

By offering burn-in systems that support boundary-scan test of DUTs, firms such as Aehr Test Systems and Unisys are pursuing high-speed structural test during burn-in. In July, Aehr Test added boundary-scan test capability to its MAX3 monitored burn-in system. The MAX3 now includes a 24M-bit-by-4-bit vector memory that can supply test vectors to an IEEE 1149.1-compliant DUT’s TAP. The Unisys Series 3000 PowerScan system supports the TAP at rates to 75 megatransfers/s and offers 48 additional channels of vector memory.

Figure 3. For at-speed, temperature- conditioned test, a thermal handler places DUTs in low-inductance test contactors such as these Johnstech Pad Series contactors, which accommodate MLF (micro lead-frame) RF devices. Each Pad Series contactor’s center MLF pad offers less than 0.2-nH inductance; peripheral pads offer less than 1-nH self-inductance and 0.232-nH mutual inductance. The devices’ –3-dB bandwidths extend to 14 GHz.

a)

b)

Figure 4. (a) A thermal-control handler such as the IHS 1000tx from Schlumberger aims to control DUT temperature during final test. (b) The IHS 1000tx responds to the dynamic power supplied to a DUT to keep junction temperatures of a flip-chip DUT within a 3°C band during test.

Thermal Control at Final Test
Burn-in isn’t the last point at which thermal issues matter during device test. Thermal control is equally important at final functional test, and thermal handlers from companies like Aetrium can thermally condition devices as it places them in test contactors. In July, Aetrium introduced thermal handlers for MLF (Micro Lead Frame) packages, and Everett Charles and Johnstech (Fig. 3) have each introduced contactors for MLFs. The Aetrium Model 5500 can handle devices throughout a three-temperature test sequence with temperature set points between –155 and +155°C.

Like burn-in sockets, test contactors must tolerate test temperatures of 150°C or higher. But because tests will be performed at rated speeds, these contactors, unlike burn-in sockets, must exhibit extremely low inductance—typically less than 1 nH, as compared with 6 nH or so for a burn-in socket. And while burn-in sockets generally must withstand hundreds of DUT insertion cycles, final-test contactors, operating through much shorter test procedures, must withstand hundreds of thousands of DUT insertion cycles.

Heating a DUT up to its rated temperature and then applying test vectors at its rated speed isn’t the ultimate answer to final test. Tight control of DUT junction temperature throughout the test can be critical to ensuring accurate test results. Accurate speed grading, for example, can only be performed when a DUT is operating at its full speed at its rated junction temperature.

Yet controlling package temperature doesn’t guarantee accurate control of junction temperatures. Engineers at Schlumberger have been promoting the significance of junction-temperature control for two years,⁵ and controlling junction temperature during test is becoming increasingly important because of increasing device speeds, the reduction of thermal mass of IC packages, and the unrealistic thermal and electrical stresses placed on DUTs by at-speed functional test.

To control junction temperature, Schlumberger developed its IHS 1000tx and IHS 1000th thermal-control handlers for characterization and production, respectively. These systems use a heat exchanger to control device package temperature; the heat exchanger responds to instantaneous DUT power levels to anticipate changes in junction temperature that would result from the DUT self-heating. The heat exchanger then compensates for those changes. For DUTs dissipating up to 100 W/cm², the systems control junction temperatures to within 3°C of a set point (Fig. 4). In contrast, Schlumberger researchers have measured more than 25°C junction-temperature overshoots upon application of 28 W of power to a microprocessor die having an initial temperature of 100°C.

What’s interesting to note is how little the test environment resembles the ultimate operating environment of the DUT. Few microprocessors will ultimately mate with a conductive heat exchanger that controls temperature to within a few degrees or reside in a chamber having closely regulated air temperatures and flow rates. Most will be exposed to varying ambient extremes. A processor in an engine control unit, for example, must be able to start a car during frigid winter mornings as well as keep that car running during blistering summer afternoons.

The emergence of test handlers and ovens with close temperature control has resulted from an effort to condense the extremes a DUT will see over its lifetime into a few hours of burn-in or a few seconds of final functional test. You’ll continue to see thermal-screening and electrical-test functions merge as vendors try to control manufacturing costs, eliminate bad devices as early as possible in the manufacturing process, and correlate electrical performance with environmental conditions. Don’t, however, expect burn-in and ATE functionality to merge into one system. Burn-in will remain the domain of hours-long thermal stress and low-frequency test, while ATE systems will handle high-speed test, albeit with increasingly sophisticated multitemperature thermal handlers. T&MW

FOOTNOTES
1. Gelsinger, Pat, “Discontinuities Driven by a Billion Connected Machines,” Plenary address at the 1999 International Test Conference. The address was printed in IEEE Design & Test of Computers, January–March 2000, p. 14. www.computer.org/dt/dt2000/d1toc.htm.

2. Hamilton, Harold E., and Charles H. Morris, “Control Chip Temperature During VLSI Device Burn-in,” Test & Measurement World, April 1999, p. 67. 

3. Nelson, Rick, “ATE Guards IC Quality,” Test & Measurement World, June 2000, p. 36. 

4. Dudinski, Frank, “Why Burn-in and Is It Necessary?” Yamaichi Electronics, San Jose, CA, www.yeu.com/banner3.htm.

5. Malinoski, Mark, et al, “A Test Site Thermal Control System for At-Speed Manufacturing Test,” Transactions, IEEE International Test Conference, 1998. pp. 119–128.

You can contact Rick Nelson at rnelson@cahners.com.