Operating-Extremes Test Improves Reliability
You can screen out abnormal devices by operating devices outside their specified voltage and temperature ranges and performing IDDQ tests.
Barry T. Mitchell, American Microsystems, Pocatello, ID -- Test & Measurement World, 11/1/2000
Exercising an IC outside of its specified operating range and performing IDDQ (or IDDS) testing can screen out devices that would fail during a QC screen or in a customer’s product.1 At American Microsystems, we have found operating-extremes testing to be an effective way to test ICs while cutting the expense of burn-in. Our experiences can help you apply the technique to your own device tests.
Before you can implement operating-extremes test methods, you should fully characterize three parameters: the VDD operating-voltage range, the propagation delay (or clock frequency), and the IDD standby current (IDDS). Perform this characterization on a significant sample of ICs that represent the expected variations in your fab process—for example, on a sample of products from three or more fab lots. Perform continual lot-summary monitoring so you can implement corrective actions for the fab process or for the test program.
Operating-extremes tests typically exist in the following forms:
1) Extreme VDD tests. Extreme-low and extreme-high VDD tests can eliminate ICs with single-transistor gate-length or gate-width abnormalities or that have resistive-contact and resistive-via defects (Fig. 1). To implement extreme VDD tests, first characterize the VDD operating range. Our 0.35-micron 3.3V SRAM functioned over a 1.9-V to 6.4-V VDD range. We chose a 2.5-V level for our extreme-low VDD test and 5.5 V for our extreme-high test.
During extreme VDD testing, apply all possible functional test patterns to provide 100% stuck-at-fault coverage. Run the extreme-low VDD test first to remove the low-VDD sensitive units from your test population. Executing the high-voltage test first can temporarily “heal” a bad unit (perhaps one with a flawed contact or one with a subtle metal bridge).
Extreme-high VDD testing can detect latent defects—including imperfections in the oxide layer and in the insulating layer between metal or poly lines—that, when subjected to voltage stress, deteriorate over time and form a conducting path between lines or layers that should remain isolated. Subjecting ICs to high-voltage stress accelerates breakdowns and eliminates weak ICs early in the test process.2
If a part doesn’t function during strobes-on extreme-VDD testing, you can apply high-voltage stress while applying functional test patterns with device outputs masked. We typically supply VDD levels at 1.5 times the VDD-high level while executing the DUT’s entire test-pattern sequence for at least 100 ms. A nominal VDD test with the error strobes enabled follows this test. Figure 2 shows a defect screened out by high-voltage stress. (The die was fully functional over the normal voltage range before being subjected to high-voltage stress. A bitmap of the failed die showed a single column failure, which we located visually, laser-marked, and submitted for FIB.)
• Learn more about Barry Mitchell's tests, read "Sample Results," below. Combining extreme-high VDD or high-voltage-stress testing with IDDQ can screen flawed gate oxide (Fig. 3). The stress voltage used should be set such that it can damage flawed oxide but leave flawless oxide unharmed. It depends on the oxide thickness and stress time. Because the damage to an oxide at high voltage is mainly due to the tunneling current flowing through the gate oxide, the stress voltage should be selected so oxide tunneling current is small in flawless oxide but large in defective oxide. Products with defective gate oxides do exhibit higher IDDQ levels after extreme-high voltage tests. The stress values of the oxides should be around 0.6 to 0.78 V/nm.3 For example, a typical 0.35-micron DUT has gate oxide thickness of 7 nm; therefore, the stress voltage should be somewhere between 4.5 V and 5.5 V. If you suspect the selected stress voltage is too high, loop a sample of parts through multiple stress cycles; then, verify that the units are still good and that IDDQ remains constant. We have looped a 1-Mbit RAM through a complete test (which included a 5.5-V test); the IC remained functional and IDDQ remained under 10 mA. Stressing the part while running the entire vector set is ideal so you can stress each NMOS and PMOS transistor. To effectively stress a NMOS transistor, hold its source, drain, and substrate at 0 V while holding the gate at the stress voltage. To effectively stress a PMOS transistor, hold its source, drain, and substrate at the stress voltage while holding the gate at 0 V. For voltage stress to be effective, your fab process developers should realize that you will use extreme-voltage tests and that your test processes cannot tolerate compromises in such transistor characteristics as snap-back voltage tolerance and hot-carrier lifetimes. 2) Propagation-delay-distribution tests. These tests employ strobe timing that falls outside the specified propagation-delay requirement in AC timing tests. We recommend a statistical approach for determining the most effective tightened strobe limit. Collect propagation data from several fab lots and plot the distributions to determine lower limits. Finally, determine a production pass/fail propagation limit at which your tester can differentiate between a normal and an abnormal product. Monitor and analyze any yield losses that result from these tests. 3) Temperature-extreme tests. We have generally found that performing wafer sort at elevated temperature (70°C to 85ºC) and then performing final test at room temperature works for most commercial-grade products. If you can’t implement extreme-voltage testing and propagation-delay-distribution testing (many analog or mixed-signal products might not tolerate such testing), then you should implement testing at two temperature extremes. If the product is specified over the commercial-grade temperature range (0°C to 70°C), and you can’t apply extreme voltage tests, try to screen at the industrial temperature range (–40°C and +85°C). Some engineers may argue that room-temperature testing should be sufficient. There are at least three arguments against this theory. First, testing at two temperatures lets you separate the temperature-dependent shifts of normal products from the parameter shifts of abnormal products (such as shifts in leakage, IDD-dynamic and IDD-static currents, propagation delay, and operating frequency). Second, new wafer-sort probers make it easy to implement hot-chuck sorting without adding costs; indeed, they may make it impossible to implement room-temperature wafer sort. (For example, the lowest set temperature for the TSK probers we use is +30°C.) Third, it is advantageous to perform overvoltage supply tests or voltage-stress tests at elevated temperature. Latch-up problems, for example, are most likely to appear at an elevated temperature, and the voltage-stress test may be more effective at an elevated temperature. 4) IDDQ tests. IDDQ testing is based on the assumption that the fault-free IDDQ of the IC under test be very small. The newer deep-submicron processes and design practices tend to increase the fault-free current, making such an assumption less accurate. At the same time, normal short-channel transistor leakage current is widely spread in the process window. For example, IDDQ typically increases by a factor of 10 when gate length changes from 30 to 50 nm. These large (and widespread) leakage currents make it difficult to perform IDDQ-sensitive measurements.4 With this in mind, you must find ways to reduce the fault-free current. The best method (and perhaps the only method available to test or product engineers) is to cool the circuit. In our deep submicron ICs, the normal leakage currents have a strong temperature dependence. W e find that leakage currents double every 15°C on our 0.5-micron and 0.35-micron process (Fig. 4).
Defective ICs have leakage currents that are not temperature dependent. For example, the IDDQ current of an IC with a resistive bridge between VDD and VSS will not be temperature dependent. Such a defective unit will likely have high IDDQ current both at elevated and at room temperatures. The IDDQ current at the hot temperature is likely to be within the normal distribution of the hot temperature IDDQ; at room temperature, however, the defective unit will have a much higher IDDQ than the normal population. Therefore, perform IDDQ testing at low or room temperature. This is not to say you shouldn’t perform IDDQ testing at hot-chuck sort. You certainly should employ a hot-temperature IDDQ test to maximize final-test yields, but the limits used at hot-temperature testing should follow the leakage-doubling factor. For example, the temperature delta between a 70°C hot-chuck wafer sort and a 22°C to 25°C ambient-temperature test is approximately 45°C (or 3 times 15°C). If you determine, for example, that the upper limit of IDDQ at room temperature should be no more than 50 µA, then the 70°C hot-chuck wafer sort limit should be 23 (or 8) times higher or, in this case, approximately 400 µA. In summary, the limit at hot temperature needs to be high enough to avoid rejecting a good unit that has a very high normal IDDQ value at elevated temperature, and the limit at room (or cold) temperature needs to be low enough to detect faults. In many cases, you will need to use empirical methods to define the proper IDDQ limit. Take IDDQ measurements on sample ICs or die from three or more fab lots and then determine the limits using a statistical method. We obtain best results when we employ the interquartile range statistic Q3-Q1:5 the distance between the 25th (Q1) and 75th (Q3) percentiles on the current-distribution plot. We use the formula Q3+1.5(Q1–Q3) to calculate the upper limit. Because leakage currents tend to scale logarithmically, we found it best to take the logarithm of Q3 and Q1 first, perform the calculation, and then take the antilog of the answer. If we don’t use logarithms, the leakage limit becomes too tight, resulting in an excessive rejection of good parts. Once again, it is important to monitor and analyze any yield losses incurred with the tests mentioned in items 1 through 5. These failures will reveal the reliability-related defects that each IC is susceptible to, so you can correct your production pro-cesses to eliminate them. Disadvantages vs. Advantages In many cases, operating-extremes testing is handcrafted, difficult to debug, and costly to monitor and analyze. Furthermore, operating-extremes testing may push your ATE to the limits of its accuracy, leading to repeatability issues and false yield busts. The costs of test exceeding the ATE accuracy and system repeatability may include system debug time, loss of engineering time, delayed customer deliveries, and unnecessary yield loss. Yet, omitting operating-extremes testing would likely be even costlier, because you could pass large quantities of nonfunctional devices to a board manufacturer or end user. It becomes exponentially more expensive if the defect is caught in the field because of increased troubleshooting time, manufacturing-line down time, and so on. Typical board-manufacturing operations are limited in their ability to screen performance-related issues. An undetected soft defect, related to inadequate operating-extremes test, could become a significant problem with the larger complex modular systems. One benefit of operating-extremes testing is that it lets you find defects at probe and then provide feedback to engineers at the fab so they can take corrective action.6 This feedback is useful for several reasons: • In many cases, the IC suppliers do not perform failure analysis on normal levels of final-test or burn-in fallout, so the fabrication engineers do not have access to the data required for root-cause corrective actions. • Fabrication engineers use wafer yields as a key indicator for process improvements. • Generally, operating-extremes failures are similar to burn-in failures or to field returns. This similarity can be exploited to provide an early-warning indicator to the IC supplier or to the customers of a potential quality problem. • Operating-extremes testing frees up valuable resources—product/test engineering, failure analysis, reliability, process engineering, and fab manufacturing support—that you can redirect to improving wafer sort yields, quality, and reliability. This also reduces time needed for getting new processes internally qualified and ready for full production. Note that it is important to monitor and analyze any yield losses incurred with operating-extremes tests. No containment plan is 100% effective; therefore, you must analyze the results and take corrective action to obtain the maximum effectiveness from these tests. T&MW REFERENCES 1. Duey, S., A. Harvath, and P. Kowalczyk, “Improved Quality and Reliability Using Operating Extremes Test Methods,” Proceedings: 1993 Custom Integrated Circuits Conference, IEEE, Piscataway, NJ. www.ieee.org. 2. Habholkar, D.B., Optimization Problems in Low Power and Stress Testing, Ph.D. Thesis, Department of Computer Science, State University of New York, Buffalo, NY, August 1986. 3. Chang, J., and E. McCluskey, “SHOrt Voltage Elevation (SHOVE) Test,” International Workshop on IDDQ Testing 1996, IEEE, Piscataway, NJ. www.ieee.org. 4. Keshavarzi A., K. Roy, and C. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs,” Proceedings, International Test Conference 1997, IEEE, Piscataway, NJ. www.ieee.org. 5. Simon, Laura, “What is the Interquartile Range?” www.stat.psu.edu/~resources/ClassNotes/ljs_12/sld007.htm. 6. McEuen, S.D. “Reliability Benefits of IDDQ,” Journal of Electronic Testing: Theory and Applications, #3, Kluwer Academic Publishers, Norwell, MA, 1992. pp. 327–335. www.wkap.nl. Barry Mitchell is senior staff product engineer at American Microsystems. E-mail him c/o T&MW: tmw@cahners.com. We employed operating-extremes test on a CMOS ROM family that was experiencing abnormally high QC fallout at cold temperatures for both commercial-grade (with failures of 400 ppm) and industrial-grade (660 ppm) products. Using a tester equipped with a bitmap tool, we analyzed the cold QC rejects and determined that the failures were single-bit failures (single bits were failing to zero, which equates a weak core transistor). Failure analysis showed that resistive contacts (due to silicon formation) were the root cause. When we implemented an extreme VDD test (in this case, 7.0 V for a 5.5-V-rated part), the same single-bit failures would reveal themselves at room temperature. We added a 7-V screen at both wafer sort and final test, and the failure rates at the QC cold test dropped to less than 30 ppm. We also employed a CMOS SRAM as an early-life qualification vehicle and as a process monitor for a 0.5-micron process. The early-life failure rate was averaging 0.35% to 0.45%. We added three operating extreme tests: an extreme low VDD test, a combination of extreme VDD test and voltage stress test (such that we could differentiate between stress-induced failures and extreme-high VDD failures), and an 18-vector IDDQ test. After we implemented these tests, there were no failures of surviving devices generated during either the early-life or long-term-life qualification and only one failure generated in subsequent tests.—Barry T. Mitchell
Figure 1. The 3.3-V (nominal) wafer pictured here exhibited many single-bit failures during an extreme-high (VDD = 5.5 V) voltage test. These failures resulted from high via-to-metal resistances due to undercut metal.
Figure 2. Here, a tungsten defect nearly shorts two metal column lines. Application of a voltage stress induced a column failure that manifested itself during a test at nominal voltage. I visually located the defect using a microscope and laser-marked it before generating this focused-ion-beam cross section.
Figure 3. The divot in silicon shown here is a problematic wrinkle in the gate oxide. For this device, a voltage-stress test induced a high I DDQ level.
This graph illustrates the IDDQ-current vs. temperature characteristic of four lots of a 0.35-micron SRAM. In general, leakage currents double every 15°C.
Sample Results
