Simulator Test Tools Speed Circuit Design

For my project—a tuning fork for the tone-deaf—I got to be my own marketing as well as design- and test-engineering departments. Negotiations between my marketing and engineering personalities (see my June staff column) yielded this design spec: The circuit would compare an input frequency with a 440-Hz reference; its full-scale range would be a quartertone above and below the reference frequency (427.5 to 452.9 Hz), and its accuracy should be within a 64th-tone (60.79 Hz).

My goal was not to demonstrate any circuit-design virtuosity—I’ll save that for my colleagues at EDN, Test & Measurement World’s design-oriented sister publication. Instead, my goal was to solve the problem using parts that appear in the standard ICAP/4 Spice-model library and that I had on hand.

Real EEs Don’t Use PLLs
My first thoughts were to employ a phase-locked loop (PLL), but I rejected that approach for two reasons: I didn’t have a CD4046B chip, the only PLL in my ICAP/4 library, and more important, a one-chip solution wouldn’t be very interesting. I wanted an approach that would combine many linear and digital components and whose accuracy and repeatability would depend on potentially unstable and drifty analog voltage levels.

I came up with the kludge represented in Figures 1 through 3. A zero-crossing detector (Fig. 1) would convert an input sine wave (Vin) to a square wave, which when high would charge an op-amp integrator (Fig. 2). Subsequently, a reference-input square wave would discharge the integrator. The integrator output voltage at the conclusion of this charge/discharge cycle would represent the difference between the input- and reference-signal periods. This level could be captured by comparators and an output latch (Fig. 3).

I made several enhancements to my basic design, because of problems I identified before putting cursor to screen and because of problems I encountered during circuit simulation as well as construction. First, I identified a shortcoming in the marketing spec—it failed to provide an update rate. I envisioned the output being a string of LEDs that would connect to the Figure 3 output latch. A once-per-half-cycle update at 440 Hz would obviously not be useful to the user.

Because the human ear does not detect sound-wave variations slower than about 12 to 20 Hz as pitch (they’re apprehended as beats), I reasoned that an update rate faster than about 20 Hz would be unnecessary. Consequently, I decided to drive the integrator for a period corresponding to several input and reference cycles. Eight cycles came to mind, as I had on hand a couple of 74HC164 8-bit serial-in, parallel-out shift registers. I initially reduced the cycle count to seven, reserving the shift registers’ eighth bit for resetting the integrator to zero after each measurement. This approach worked fine in the simulation, but the integrator did not seem to reliably reset within the allotted time at worst-case reference-to-input phase relationships in my breadboarded version, so I allocated an additional cycle for circuit reset.

I realized that reducing the number of cycles over which the integrator operated would place more stringent accuracy demands on the comparator-based level detectors in Figure 3. I was still pretty fuzzy on what a meaningful refresh rate would be anyway, and might find myself adding additional shift registers, so an initial choice of six cycles seemed as good as seven or eight. Further, I could see that the simulator would be of little help in this regard; I would ultimately have to put my marketing cap on and convene a focus group to evaluate the working prototype’s user interface. The ICAP/4 library doesn’t include focus-group models.

My eight-cycle approach—six for measurement and two for reset—would provide a refresh rate of 55 Hz at A440—higher than necessary, yet high enough to possibly extend the allowable reference frequency down at least one octave. I tabled further consideration of update rates pending focus-group results.

My Initiation as a Spice Boy
My next step was to capture the schematic from the notes and block diagrams I had jotted down. ICAP/4’s SpiceNet schematic-capture program, although it lacks features like rubber-banding that you’ll find in dedicated schematic programs, was easy to use, and I was able to populate my screen with components and wire them up quickly. My first effort at simulation was another matter altogether. I set up the reference voltage as 440 Hz and the input as 445 Hz and expected to see the results shown at the right-hand side of Figure 3: The Above_quartertone_high testpoint remaining low with the other three transitioning high at the end of the measurement period.

Instead, I was inundated with error messages, including “Node 15 can’t be analog and digital!” That message continues to stump me; it occurs whenever I connect a 74HCT14 Schmitt-trigger inverter to analog or other digital CMOS parts. I’ve referred this problem to the factory and meanwhile am using ’04 inverters instead of the Schmitt-trigger versions, although the latter seem perfectly happy to promiscuously connect to non-Schmitt-trigger parts in the real world.

I then began breadboarding the circuit, figuring I could defer simulation and its error messages until I had a working physical model. That approach, too, proved problematic. My input-signal circuitry through the zero-crossing detector worked fine, but my REF6 signal refused to stay high for six reference cycles.

Defeated on two fronts, I returned to the simulation and soon got the knack of making sure that diodes had part numbers assigned, that nodes weren’t left hanging, and that ICs had supply voltages properly connected. The simulation soon worked fine, as long as I avoided using Schmitt triggers.

At this point, I employed the two simulation modes that were most helpful in troubleshooting my prototype: AC and transient analysis. I used AC analysis to characterize the bandpass filter (Fig. 1). The simulator’s swept-parameter feature made it easy to determine the effect of various component values on filter response. Figure 4, for example, shows the frequency response for five values of C2.

I next initiated transient analysis. To set up the transient simulation in ICAP/4, I specified a time step size (for instance, 10 ms) and a total analysis time (about 20 ms to cover the eight-cycle—at 440 Hz—measurement and reset period). The simulation waveform vignettes in Figures 1 through 3 and the Intu-scope display in Figure 5 show simulation data from 3 to 23 ms; I suppressed display of data for the first 3 ms as nothing much of interest happens then.

The simulator’s transient analysis was helpful in characterizing the integrator and level-shifter’s performance, making it easy to ensure that the Vint signal remained within the 67.5-V limit mandated by the analog switch. Transient analysis was also helpful in fine-tuning a quick-and-dirty RC one-shot (which synchronizes the IN6 and REF6 signals to within one reference cycle) and two RC delays that provide adequate time for the output latch to acquire valid data.

These delays establish a “back porch” on the output voltage signal (beginning at 18.2 ms in Figure 5 and extending for about 500 ms) that allows adequate time for the output latch (Fig. 3) to acquire valid data. In other cases, though, the simulation’s slowness (about 3 min to simulate 20 ms of tuning-fork operation on a 233-MHz Pentium system) prompted me to experiment on the breadboard. For example, I developed a mental block about the shift-register reset circuitry in Figure 1 and found it much quicker to plug in real NAND and NOR gates to determine that a NOR gate was what was wanted. In fairness, I should note that had I entered my design in multiple subcircuits, I could have simulated subcircuits representing groups of components in isolation, speeding the simulation.

Having successfully simulated the circuit, I returned to the breadboard and the problem of the REF6 signal not remaining high for six reference cycles. At this point, I was deriving the reference voltage by using a PC’s line-out audio signal generated from a 440-Hz .WAV file to drive a comparator-based zero-crossing detector. Not having expected to need a 100-MHz scope to trouble-shoot this audio circuit, I at first didn’t notice the 200-ns glitches on the comparator outputs. The reference shift register did see these glitches, however (as I finally did after connecting a 100-MHz scope), and dutifully counted each one. Adding a differential input and bandpass filter between the PC and the reference zero-crossing detector solved this problem (Fig. 6). Although the simulator does not have a “noisy PC input” model, it does include various noise modeling features, but I am still attempting to duplicate in the simulator the real-world results I was seeing.

In one other area, the real world presented a problem that I didn’t see in the simulation. National Semiconductor’s data sheet for the CD4066B analog switch intimates that the part, when powered by a unipolar supply, will reliably switch 67.5-V analog voltages. The replacement-part NTE Electronics switches that I used, however, began conducting when either switch input/output terminal reached –1 V. This characteristic distorted the negative-going portion of the Visrc waveform and prevented the integrator from accurately developing negative voltages (which should appear when the input frequency is higher than the reference frequency). Adding a –5-V supply for the analog switches solved this problem.

With a working simulation and breadboard, it became time to investigate the effect of component tolerances on circuit performance. The back-porch voltage is critical. For a 440-Hz reference and 445-Hz input, the integrator back-porch level (at node 129) is nominally –542.71 mV. To investigate the effect of component tolerances on this value, I ran an RSS (root summed square) analysis that acquired the integrator output voltage at 18.4 ms.

RSS runs a circuit simulation for each component having a tolerance and measures that component’s effect on the measurement or measurements the simulator is set up to acquire. An RSS simulation is time consuming (about an hour for this circuit on a 233-MHz Pentium PC), but it’s hard work only for the computer, not for me. The results show that 2% resistors and 5% capacitors could cause the integrator back-porch voltage to range from –1.2954V to 210.02 mV—a wide range that would mandate time-consuming tweaking of the level detectors in Figure 3. (You can view the complete RSS report.) 

The Cliffhanger
RSS analysis, however, presents worst-case results, and it’s valuable to ask what the chances are of obtaining these results in a production version of the circuit. In a random substitution of parts on my breadboard, I saw nowhere near the variation calculated by the RSS simulation. In a subsequent article, I will discuss Monte Carlo analysis and other simulation approaches to addressing this question. In addition, I will present a circuit fault tree and discuss the development of a final product acceptance test. And, of course, I will present my focus-group members’ comments on how pleased they are with product performance. T&MW

Copyright 1999, Test & Measurement World. Published by Cahners Business Information, Newton, MA.