| As the frequency of ADCs increases, the
challenge of evaluating the performance of devices in production-scale quantities becomes
progressively more difficult. One difficulty stems from conventional modes of testing
ADCs, which, at higher frequencies, tend to reflect the combined performance of the device
and the test hardware, rather than the performance of the device alone. Another difficulty involves the inherent differences between
production-testing and bench-testing methodologies. In production test, optimization of
one test can degrade another test that must be performed on the same device.
By contrast, in bench testing, you can employ one set of
instruments to measure one parameter and then decide to use different equipment to measure
another. Some tests are rarely performed in the lab: For example, bench tests seldom
include continuity tests, whereas production tests do. In production testing, the extra
interface circuit needed for this test will compromise the noise performance.
Overcoming this condition requires improvements in both the
quality of the test signal into and out of the device and the stability of the test clock.
At Teradyne, we developed an approach for optimizing signal quality by stabilizing the
clock when testing high-speed ADCs.
 |
| Figure 1. Test equipment can be a
significant source of noise. Analysis of noise origins helps you separate the noise
performance of the DUT from that of your ATE. |
Noise Factors During Testing
To measure the signal-to-noise ratio (SNR) accurately, you must generate the most perfect
test signal possible, and then use the DUT to capture this signal. Ideally, the test
signal should be a perfect sine wave, but the quality of a sine wave generated by test
equipment is diminished by these factors:
- noises from the test equipment, including those caused by
improper interface design or physical limitation (such as amplified thermal noise from the
signal source or spurious signals from the frequency synthesizer),
- jitter related to the clock (the relative jitter between the
test signal and the clock signal provided by the test equipment), and
- harmonics (the test equipment itself will generate harmonics
due to nonlinear distortion).
If you minimize these test-system-generated noise
sources, you can more accurately measure the noise sources associated with the DUT itself:
- noise generated by the DUT’s input circuit,
- noise caused by the DUT’s aperture jitter, and
- noise caused by the DUT’s nonlinear distortion. (The
noise caused by lower-order nonlinear distortions is often interpreted as harmonics. An
ADC can have a very high order of nonlinear distortions, some of which will manifest
themselves as spurious signals during spectrum analysis.)
These six tester and DUT noise sources contribute
to SNR as shown in Equation 1:
where
N = the DUT’s number of bits,
Jtrms = relative rms jitter of the clock signal and the test signal,
Noisetrms = rms noise of the test-signal source,
Fanalog = test-signal input frequency,
Jrms = intrinsic rms jitter of the ADC,
e = average DNL of the ADC, and
Noiserms = intrinsic rms thermal noise of the device input.
To accurately measure the last three (DUT-generated) noise
characteristics, we built a test system (Fig. 2) to minimize the first
three (tester-generated) noise figures. The system comprises a mixed-signal tester
equipped with the following instruments:
- a clock instrument, providing less than 3-ps jitter at
the high end of the frequency range—a key element to fast ADC testing;
- a VHF continuous and arbitrary waveform generator,
providing about 55-dB SINAD and 2-ps jitter (under the conditions the tests were
performed), which generated the test waveform signal for differential and integral
nonlinearity, signal-to-noise, signal-to-noise-and-distortion, and distortion tests;
- high-speed digital channels, for capturing the
device’s digital output, differential gain and phase programming, pin open-short
tests, DUT digital-driver-level tests, and clock-level tests; and
- power-supply sources, which provided power to the DUT
and also were used to measure DUT power consumption.
 |
| Figure 2. This ADC test interface can
evaluate ADC parameters such as noise, offset, linearity, and distortion. |
We also employed a device
interface comprising the following components:
- a test socket impregnated with abrasive gold-plated
diamond particles to ensure optimal electrical contact;
- a 5-in. circular PCB, for mounting the test socket and
other sensitive components connected to the DUT;
- a device interface board (DIB), for connecting the test
head to the 5-in. PCB and providing a wiring area for submodules, including a clock
circuit, a programmable filter module, a power-supply circuit, and a module we developed
to stabilize the clock; and
- a test head, containing electronic circuits that
condition the test signal and which need to be very close to the DUT. (A mixed-signal
tester, such as I used, can integrate an extensive range of instruments. As a result, the
tester cannot be built in a single compact unit. Our tester includes two parts: the test
head and the tester mainframe, which incorporates all other components of the test
system.)
We improved the performance of our test system by
employing
- filters to reduce test equipment noise, relative jitter,
and harmonics;
- a smart digital interface, carefully maintained power
supply, and experimentally optimized interface board to reduce interface noise;
- a jitter reduction module (patent-pending) and divider
to reduce relative jitter between the test signal and the clock signal; and
- noise calibration to separate device input circuitry
noise and remaining noise inside the filter bandwidth. (For a further explanation of how
we modified our tester, see “Optimizing Test Hardware Performance,”)
Using this setup, we subjected commercially available 12-bit 41- and 65-MSPS
ADCs to the following AC tests:
- SINAD, THD, SNR, NOEB and SFDR tests;
- gain, offset, and linearity tests;
- differential gain and phase tests; and
- intermodulation distortion tests.
Of these four groups of tests, the SINAD, THD, SNR, NOEB and
SFDR test set (predominantly dynamic in nature) showed the most significant improvements
as a result of the filter, digital-interface, jitter-reduction, and noise-calibration
enhancements we made to the test system. (Note: Space does not permit a full presentation
of results for the complete suite of tests. If you would like to see the complete results,
please send me an e-mail message: fang.xu@teradyne.com.)
SINAD, THD, SNR, NOEB, and SFDR Results
With the device clock running around 41-MHz, we performed the SINAD, THD, SNR,
NOEB, and SFDR tests using two different analog inputs: 19.5-MHz and 70-MHz sine wave at
–1 dBFS (dB full-scale). The sine waves generated by the VHF source instruments were
filtered by a narrow bandpass filter to produce as perfect a test signal as possible. A
Fourier analysis of the DUT digitized sine wave (Fig. 3a) provided
information on the fundamental power, the harmonics, and all other unwanted components.
 |
 |
| Figure 3. (top) Fourier analysis of a
captured signal provides information on the fundamental power as well as on the harmonics
and all other unwanted components. (bottom) Noise calibration results in a Fourier
analysis that more accurately reflects the device under test. |
Our next step was to explicitly derive THD,
SNR, SINAD, NOEB, and SFDR from the digitized DUT output. The total harmonic distortion
(THD) represents the ratio between the fundamental power and the power of all harmonics.
The signal-to-noise ratio (SNR) is the power ratio between the fundamental and the sum of
all random noise power excluding harmonics. SINAD represents the ratio of the signal to
all unwanted components: noise plus harmonics. The number of effective bits (NOEB) can be
calculated from SINAD as follows:
NOEB = (SINAD – 10log1.5)/(10log4)
The three ratios—SINAD, SNR, and NOEB—must be
calculated with care taken to first remove the fundamental power to enhance the
computational precision. Otherwise, you would see a 3-dB “improvement” to the
SNR and SINAD. The spurious-free dynamic range is the range from the fundamental to the
highest spurious (noise or harmonics).
From the Fourier analysis of Figure 3a, you can see that the
bandpass filter reduces the noise outside of its passband. It cannot do anything to the
noise within the passband. So, in this spectrum, the noise floor around the 19.5-MHz
carrier is higher than in the other region. This additional noise reduces the measurement
dynamic range and degrades the repeatability of the test.
An intelligent noise-calibration technique can overcome this
limitation. To implement this technique, our test program used the noise floor itself as a
reference—digitizing the same signal 100 times and generating an averaged spectrum
free from run-to-run noise.
This averaged spectrum is then subjected to digital signal
processing to make a spurious-free smoothed-noise-floor spectrum. Notice the white curve
in the spectrum (Fig. 3a). The noise level of the flat part of the noise floor serves as
the noise reference. This noise-floor spectrum serves to compensate the captured spectrum
during test (Fig. 3b). This calibration improves SINAD measurement by 3-dB and reduces the
standard deviation from 0.16 dB to 0.07 dB. It also provides increased sensitivity for
detecting a noisy device.
Using these procedures, we significantly improved the signal
quality and clock stability of our ADC test system. These improvements have enabled us to
evaluate the performance of production-scale quantities of state-of-the-art, high-speed
ADCs with a higher degree of precision than previously possible when using automated test
equipment. T&MW
Fang Xu, Ph.D., is a senior application engineer in Teradyne’s Fast Converter
Test Expert Team. He is a member of the team’s Test Assistance Group. He alternates
between Paris and Boston. fang.xu@teradyne.com.
Optimizing Test HardwareTo optimize test-system performance when testing fast ADCs, we made the
following modifications to components found on either the 5-in. circular PCB or on the
device interface:
Hardware Enhancements on the 5-in. PCB
O Digital
output interface circuit. An ADC’s digital outputs have limited
current-driving capability, and uncontrolled output source or sink currents can cause the
DC output voltages to wander toward DVCC or DGND. To control these currents, which would
otherwise disturb the entire device, we employed damping resistors on the 5-in. PCB to
limit peak currents when the test equipment’s capacitive loads on the DUT output pins
charge and discharge.
O Device
input interface circuit. When performing the input-pin continuity test and
the differential gain and phase measurement, DC instruments and high-speed digital
instruments must connect to the device pins. Because the DUT is sensitive to noise, these
connections require isolation—typically effected with a parallel LC connection. We
enhanced isolation by inserting a relay in series with the LC network to minimize
capacitive cross-talk to the input within the AC band of interest.
O Power-supply
circuit. An ADC usually has four power-supply pin groups, with some pins
dedicated to the analog ground and others to the digital ground. Although the analog
ground pins are not internally wired with digital ground pins, they usually must be
connected outside of the device at some point. Our 5-in. PCB established these connections
and included low-self-resonant-frequency decoupling capacitors connected from each supply
input to the corresponding ground pin.
Hardware Enhancements on the Device Interface Board
O Clock
circuit. The high-speed digital channels in our mixed-signal tester provided
excellent edge-placement flexibility, but at the expense of relatively high jitter. The
clock instrument we chose for our ADC testing exhibits a few picoseconds of jitter from 50
MHz to 400 MHz, with jitter decreasing as the clock frequency increases. Therefore,
running the clock at a high frequency and then using a low-phase-noise divider to generate
the DUT-required clock signal improved the jitter performance. We ran the clock at 328 MHz
and programmed the divider ratio according to the test being run—for example, a ratio
of 16 for linearity tests, and a ratio of 8 for other tests.
O Jitter
reduction module. For further improvement, I developed a jitter reduction
module (patent-pending), which we combined with the previous divider-based technique. A
fixed-frequency passive device, this module averages signals from consecutive clock
periods to reduce clock jitter by at least 30% to as much as 85%. Despite the
module’s fixed frequency, the clock frequency may be adjusted by changing the divider
ratio. As an example of the module’s potential, I have generated 41-MHz and 20.5-MHz
clock signals from a clock running at 328 MHz. The real jitter amplitude appears to be in
the 1-ps range, as I have only observed 2-ps rms jitter, including the 1.3-ps typical
trigger jitter of the instrument.
O Programmable
filter module. The tester’s VHF instruments generate a signal with an
80- to 90-dBc noise floor. These instruments are specified for approximately 70-dBc
harmonic distortion. Without signal processing, this performance is inadequate. However,
the use of narrow-bandpass filters (implemented in a module comprising commercially
available fixed-frequency filters, relays, and an LC channel-separation tree) results in a
higher signal-to-noise ratio and lower harmonic level.
The filter module has two inputs: each can be wired to a VHF signal source. It
provides two or three relay-programmable VHF filters and a bypass path to the output of
the module. Programming tuning frequencies by a combination of manual and relay switching
optimizes performance, flexibility, and reliability. (We employ the manual switching only
when we must to test a different part type at different frequencies, resolving the
tradeoff between module complexity and the flexibility to adapt it to changing test
requirements.)
Instead of using relays, the LC channel-separation tree routes a sine wave of
a specific frequency directly to the filter input. Other unused branches of the tree
exhibit high impedance for that sine wave. All the filter outputs are connected through
low-capacitance relays so they can be tied together to simplify the circuit.—Fang Xu
|
|
