Boundary-Scan Software Aids PCB Evaluation

Need more information? Read our Product Survey Chart
for Representative Boundary-Scan Software Tools

Boundary-scan circuitry includes scan cells inserted in series with each I/O pin of an IC. A single scan cell can serve a basic unidirectional pin. Three-state and bidirectional pins require more cells (Fig. 1). During normal operation, the cells are transparent to the normal flow of data between an IC’s data pins and its internal logic. In test mode, scan-cell latches provide the data, either to exercise internal chip logic or to drive an output pin. In the latter case, a test system can probe the other end of the PCB trace to which that output pin connects in an effort to verify trace continuity.

The scan-cell latches receive their test data by means of the four-pin test-access port (TAP) defined in the IEEE 1149.1 standard.2 The pins include a test-mode-select (TMS) pin, a test-clock signal (TCK), and test-data input (TDI) and test-data-output (TDO) pins. When asserted, TMS enables the scan circuitry on each I/O pin of a boundary-scan-compliant DUT (for example, by putting the switches in Fig. 1 in the lower position). With TMS active, TCK clocks data serially into TDI, from which scan-cell latches acquire their data. TDO provides a path to the TDI of additional ICs on a PCB.

During test, the TAP signals are exercised by TAP controller hardware, available from a variety of firms.3 The TAP also can serve to carry programming information into PLDs, allowing simultaneous testing and programming—called in-system programming (ISP)—of PCB-mounted PLDs.4,5

Indeed, PLDs are a prime target for boundary-scan techniques, and PLD makers including Altera (San Jose, CA) and Xilinx (San Jose, CA) offer tools that help implement boundary-scan circuitry within their chips. Xilinx, for example, has released a Java application programming interface (API) for boundary scan as part of its Silicon Xpresso initiative announced last fall.6 The free Xilinx software package includes a reference implementation of the API, plus source code and Xilinx XC9500 CPLD algorithms that use this API. It also includes a translator that accepts boundary-scan descriptions in serial vector format (SVF) to create Java API-based applications.

In an effort to establish a standard file format for ISP, Altera freely licenses its Jam programming and test language. Jam includes two software components: a Jam composer that writes the Jam file required to program a specific design into a specific device, and a Jam player that interprets the Jam file and programs the target device.

Corelis has added support for Jam to its ScanPlus boundary-scan development, manufacturing, and field-service-test systems. The platform-independent Corelis ScanPlus software (which includes a Jam Player) can program onboard devices such as Altera’s MAX 7000 and MAX 9000 chips using Corelis JTAG controllers for the ISA bus, the PCI bus, the PC Card bus, or LAN.

Of course, boundary scan is not limited to PLDs; you can employ IEEE 1149.1 techniques on any digital part you design. A variety of software tools (see the product survey chart) can help you implement boundary-scan circuits in your designs no matter what format your design data is in—including EDIF, Verilog, VHDL, or proprietary netlist formats.

Traditionally, boundary-scan testing has been the domain of test and production engineers wishing to check the integrity of assembled PCBs by using the built-in test possibilities offered by JTAG-compliant ICs. This has required them to follow a formal test-development program involving ATPG tools that required cryptic netlist and component data formats.

JTAG Technologies is trying to make boundary-scan test easier for designers and test engineers to use by enabling access to a PCB’s boundary-scan features via an interactive Windows GUI. Its ActiveTest software hides the details of TAP states, BSDL data files, and serial shift sequences.

By reading an EDIF 200 netlist of your design along with a list of JTAG-compliant parts, ActiveTest presents a summary of PCB nets, highlighting which nets can be accessed through boundary-scan and indicating whether a pin is input only, output only, or bidirectional. Test patterns can be assigned to groups of nets using binary, hex, octal, or decimal bases. Vectors are then assigned a direction and can be executed in a single step or continuous loop modes. Logic-analyzer-style state or timing diagrams then can be used to display vector updates and vector captures. T&MW

FOOTNOTES
1. “Design Techniques Ensure Testable SOCs,” T&MW, September, 1999, p. 32.
2. 1149.1 IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE, Piscataway, NJ, www.ieee.org.
3. “Boundary-Scan Tools Keep Pace with Device Innovations,” T&MW, November 1998, p. 41.
4. “Careful PCB Layout Enhances Onboard Programming,” T&MW, January 1999, p. 49.
5. “Design a Production Test Strategy for PLD-based PCBs, T&MW, March 1999, p. 37.
6. “Initiative Moves Boundary-Scan Tool to Web,” T&MW, October 1998, p. 6.