RDRAMs Benefit from High-Speed Testers

As RDRAMs move into PCs, RDRAM test procedures must become more stringent.

Chris Mack and Wajih Dalal, Schlumberger Automated Test Equipment, San Jose, CA -- Test & Measurement World, 11/1/1999

RDRAMs promise to boost personal-computer performance as they make inroads into the PC marketplace. For the test engineer, RDRAMs represent a whole new memory architecture. Old test methodologies and equipment will not suffice.

Memory manufacturers face a dual problem: First, the architecture of RDRAM devices demands a completely different testing strategy, and second, the sheer speed and accuracy requirements for RDRAM testers are far more stringent than they were for test equipment for previous DRAM generations.

For testing those previous, conventional memory generations, manufacturers took advantage of direct parallel access to a DRAM chip’s memory array through relatively straightforward address- and data-generation schemes. Conventional DRAMs have steadily increased in size and speed. In the last decade, they have grown from 1 to 64 Mbits with speeds increasing from 30 to 200 MHz. RDRAM, however, has raised the test speed and accuracy requirements to new heights. In an RDRAM device, the conventional device’s parallel-access architecture gives way to a serial bus structure with a logic interface. An RDRAM tester must test the serial interface logic at 800-Mbps to 1-Gbps rates as well as be able to test the embedded SDRAM memory array (Fig. 1).

Figure 1. (a) Previous DRAM generations presented relatively simple address- and data-generation tasks to a tester. (b) An RDRAM, in contrast, requires direct SDRAM array test as well as at-speed interface-logic and array test.

New Test Priorities
When RDRAMs were primarily used in game consoles, accuracy wasn’t a big issue. If a faulty device slipped through, probably the worst thing users experienced was a dropped pixel in video-game graphics. When RDRAMs were used in very high-end servers, the volumes were so low and the margins so high that a long testing cycle did not have much impact on the bottom line. But in the high-volume yet demanding PC world, you can neither compromise accuracy nor tolerate low throughput.

In general, the less accurate the tester, the harder it is to tell whether the part tested can really run at speed. As device speeds increase, tester inaccuracies raise DPM (defects per million devices) levels and depress yield. Until now, testers for most memory applications have been accurate enough to let you make credible judgements about device speed. RDRAM devices, however, require speeds three to four times faster than the basic rates of current-generation memory testers.

The key figure of merit for a RDRAM tester is edge-placement accuracy. A DUT’s propagation delay has a certain distribution that’s a function of the fabrication process and the VLSI design (Fig. 2). The more mature the process gets, the tighter the distribution becomes. Furthermore, the more accurate the tester is, the tighter the overall-timing-accuracy (OTA) window becomes, and fewer good parts get rejected.

Figure 2. Lower tester accuracy results in a wider uncertainty box, resulting in lower yields and more DPM. Loosening the test limit moves the uncertainty box to the right, improving yield but increasing DPM.

Because no tester is perfect, you must establish a guardband to account for tester uncertainty, which corresponds to OTA. You then use the guardband to establish the edge-strobe placement. Assuming a normal distribution for device propagation delay, a 30-ps difference in tester accuracy would result in a 12% yield improvement for an 800-Mbps part (Fig. 3). If an RDRAM device sells for $15, and each tester processes 10 million devices per year, then a 30-ps accuracy improvement results in yield loss recovery of $18 million per tester per year. To look at it another way, each picosecond of tester-accuracy improvement results in an extra $2 million profit.

Achieving Accuracy
To realize those profits, RDRAM manufacturers need the organization and tools required to achieve the necessary levels of accuracy. From the beginning of the design process, you as a test engineer must be in the loop, working closely with your peers in design, process, and product engineering. Information on device design, validation, and characterization must flow among all team members from the first day. All members must understand the effects of design and layout on accuracy as well as on the appearance of defect mechanisms. They must also take into account the thermal-density, noise, and cross-talk effects for which high-speed testers must compensate. Keep in mind that you’ll need to test RDRAMs at or beyond rated speed. To guarantee that an 800-Mbps chip will run at full speed, you’ll need to test it at least 10% faster within a tight timing-accuracy window to ensure adequate margins in accordance with Rambus Signaling Level (RSL)1 voltage specifications.

Figure 3. This graph plots yield improvement against tester accuracy at different DPM levels. Actual yield approaches ideal yield as tester accuracy improves.

Your tester will require high-bandwidth cabling and cable-compensation circuits that maintain signal integrity and accuracy to the test head. The test-head interface should provide tightly controlled impedances to DUT pins, with contact points minimized to reduce lumped and distributed capacitance. Choose very low inductance (less than 1 µH) device test sockets, and be sure your load-board layout follows transmission-line rules to protect test signals and minimize crosstalk.

As production ramps up, you’ll need a tester that maintains the requisite accuracies and speeds when a handler is docked to the test head. The docking mechanism’s reliability and repeatability is critical to maintaining accuracy across the 8 or 16 parts tested in parallel on one head. In addition, ensure that you can maintain 1008C device die temperatures at all test sites.

High-accuracy ATE reduces the number of test systems you need, thereby cutting the overall cost of test. Conversely, throwing extra test systems at a device that was not designed with your involvement is far from an optimal approach. Communication among design, production, and test engineers—plus the ability to communicate device data among design, characterization, and test tools—is the key to success. T&MW

Chris Mack is product marketing director for memory test systems and Wajih Dalal is field marketing manager at Schlumberger Automated Test Equipment, San Jose, CA.

FOOTNOTE
1. Rambus RDRAM Data Sheets, www.rambus.com/developer/support_rdram.html.