Integration Shrinks Level-Setting Circuitry
DAC-per-pin and improved sample-and-hold architectures offer options for ATE pin electronics.
Albert O’Grady, Analog Devices -- Test & Measurement World, 12/1/1999
Complex test-and-measurement systems often must provide between 7 and 13 voltage levels to each of as many as 1000 pins per system. Recent advances in mixed-signal IC design provide the integration necessary to reduce both the PCB space and cost of implementing level-setting circuitry for each pin in ATE systems.
The current market demands increased ATE capability at a reduced cost per pin, forcing test-equipment designers to look for new ways to set voltage levels and thresholds for functional and parametric testing. Level-setting functions provide DC voltages that control the pin-driver, active load, timing deskew, window comparator, and parametric-measurement units. They define the stimulus to the DUT (device under test) and set acceptable limits for DUT performance.
The increased complexity of IC design demands that the test equipment itself become faster to accommodate more test nodes. Each pin on a test system is now a complete tester with many programmable stimulus and measurement capabilities.
Advances in device architectures and process technology have enabled commercially available devices to meet the needs of ATE manufacturers within the confined spaces of a test head. Two different approaches—DAC-per-pin and sample-and-hold—offer distinct levels of performance and cost.
ATE System Overview
Figure 1 shows a typical block diagram of the pin electronics found in an ATE system’s test head. This block repeats for each pin in a high-performance test system. The circuitry at one pin in a digital tester has four distinct sections:
- a functional/dynamic pin driver,
- a functional pin detector,
- a dynamic pin detector, and
- a static/dynamic active load.
In normal operation, each of these sections requires different voltage levels.
The pin driver requires two voltages (VIH and VIL) to define the high and low levels applied to the DUT to simulate a digital input. If the DUT pin acts as an output, the signal from the DUT goes to the pin detectors to test output levels and dynamic parameters. The functional pin detector uses programmable reference voltages VOL and VOH and two comparators to determine if the DUT output voltages lie within the limits set by the ATE program at the pin-detector DACs. The active load supplies a programmable current source or current sink to the DUT.
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| Figure 1. ATE systems include many level settings in a typical application. Various voltages and currents (whose symbols are shown in red) in the active-load, pin-driver, and comparator circuits require level setting in the application represented here. |
A diode bridge and three settings control IOH, IOL, and VMID during performance testing. IOH is the current flowing from a digital output when the input conditions configure a logic high output. IOL is the current flowing into a digital output when the input conditions configure a logic low output. VMID is usually set at (VIH+VIL)/2 and determines the direction of current flow for IOL and IOH. IOH is sourced from the output when VMID is less than VOUT of the DUT. IOL sinks into the digital output if VOUT is less than VMID.
The dynamic pin detector used in timing tests employs a DAC and a comparator. The detector compares the output signal from the DUT with a trip voltage set by the DAC to measure risetimes and falltimes, propagation delays, and setup-and-hold times. When measuring risetimes and falltimes, the ATE software sets the DAC to 10% or 90% of the voltage level of the DUT output.
ATE systems also use level-setting devices in timing-deskew circuits (Fig. 2). Because not all signal paths between the signal-source and the pin-driver circuitry present the same impedance, edges from signals are sloped at different rates. But simply squaring up the signal with a buffer may lead to timing errors between the signals. Using a DAC and a high-speed comparator at each pin driver will let an ATE program effectively remove any skew errors. The voltage at the comparators’ inverting input controls the comparator trip point. Adjusting the trip-point voltage in turn adjusts the comparator’s output timing relative to other comparators.
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| Figure 2. A level-setting DAC or sample-and-hold amplifier and a high-speed comparator can implement timing deskew. |
In all, each pin in the test head of a high-performance test system might require 13 level settings. High-performance test systems contain up to 1000 pins, thus requiring up to 13,000 levels to be set. These systems also set voltages using highly accurate DACs, with one DAC dedicated to each level setting. In contrast, lower-cost VLSI and mixed-signal-testers typically use only one DAC in association with a demultiplexer and a sample-and-hold amplifier (SHA) to set up the levels on the system.
DAC-Per-Pin Architectures
A typical ATE setup could include 14-bit DACs. Figure 3 shows a circuit with four of the eight channels of a 14-bit DAC configured to set up VIH and VIL on a pin driver and two other channels configured to set up VOH and VOL for a window comparator in an ATE circuit.
In the Figure 3 circuit, the upper voltage reference generates the references for the 14-bit DAC. In this configuration, the reference generates the VIL and VIH voltages for the pin driver. You can null any offsets associated with pin-driver electronics by adding an offset at the DUTGND AB pin of the 14-bit DAC. The bottom reference sets the trip points for the window comparator. In this configuration the circuit sets the reference voltages with respect to DUT ground, and the output will vary from –10 V to +10 V with respect to device ground. As an alternative, you could generate programmable references using 8-, 10-, or 12-bit DACs.
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| Figure 3. This level-setting application employs a multi-DAC chip in a DAC-per-pin architecture. |
SHA Architectures
The sample-and hold implementation (Fig. 4) is less expensive than one that requires multiple DACs, especially as the number of channels required increases. The ATE transfers a digital value to the 16-bit DAC and then selects the appropriate SHA.
When the DAC settling time and the SHA acquisition times have elapsed, the ATE switches the SHA into hold mode, which maintains the “held” voltage level for as long as needed. The ATE selects each SHA in turn and uses the DAC to set the SHA’s voltage to the level needed by the system. The outputs from the SHA drive the various level settings required within the test head.
The acquisition time, droop rate, and pedestal error of the SHA limit system performance to 10- to 11-bit accuracy. For a DAC having a 1-ms settling time and an SHA having a 2.5-ms to 0.1% acquisition time, the circuit limits throughput to 285 kHz per channel. Because the circuit loads the SHA sequentially, the time required to set all voltages (system acquisition time) equals the SHA acquisition time multiplied by the number of channels.
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| Figure 4. A single DAC and multiple sample-and-holds can provide level setting in low-cost VLSI and mixed-signal testers. |
Once an SHA is deselected, the input bias current of the output amplifier starts to discharge the hold capacitor. The ATE must continually refresh the SHAs to prevent the output voltage from drifting outside a predetermined level.
For example, assuming a 40-mV/s droop rate, a minimum refresh rate of 10 ms will prevent the output voltage from drifting by 0.5 LSB in a 12-bit system with a full-scale voltage of 3 V. For 10-bit accuracy, the minimum refresh rate is 60 ms, which becomes the limiting factor on the number of channels that designers can incorporate within the test system. This method of implementing the level-setting function has high overhead in terms of throughput time and software control. There is also the pedestal error due to charge injection within the sample-and-hold that needs to be factored into the design-error budget.
External hardware filters (not shown in Figure 4) remove glitches from the outputs. Thus, when the ATE updates the SHA, glitches won’t generate false triggers in comparator circuits. The key advantage in using SHAs is the cost per channel, about $1, when compared with up to $3 using a dedicated DAC per level.
With the increasing number of pins per test head and the number of level sets per pin continually increasing, the board space required to house the electronics becomes an issue. This has driven manufacturers to put more channels on each chip and to increase performance in terms of acquisition time, droop rate, and pedestal error.
Newer sample-and-hold designs offer infinite hold capability, eliminating the droop and pedestal errors associated with conventional SHAs. Infinite sample-and-hold eliminates the need for continually refreshing the output and removes external hardware filtering requirements, allowing for faster throughput.
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| Figure 5. This level-setting system configuration in the 32-channel AD5533 employs infinite sample-and-hold devices. |
Figure 5 shows one channel of an integrated infinite sample-and-hold with an output voltage level translation function. The SHA samples an analog input voltage on the common input pin, VIN, and converts it to a digital word. You can think of the SHA as an ADC on the VIN input and a DAC on each of the 32 outputs operating with 14-bit resolution.
Because the channel output voltage is effectively the output of a DAC, it has no droop associated with it. The output voltage remains constant until a new voltage is acquired on this channel. The allowable output voltage span is 10 V. In general, the output voltages required in ATE systems range from –2.5 V to +7 V in level-setting applications. A dedicated onboard DAC allows the ATE to program an offset voltage to properly set up the output voltage range. T&MW
FOR FURTHER READING
“Octal 14-Bit, Parallel Input Voltage-Output DAC” (AD7841 data sheet).
“Octal Sample-and-Hold with Multiplexed Input” (SMP18 data sheet).
“32-Channel, 14-bit Voltage Out DAC,” (AD5532 data sheet), www.analog.com/products/descriptions/AD5532.
“32-Channel, Infinite Sample-and-Hold ” (AD5533 data sheet).
Albert O’Grady is an applications engineer at Analog Devices, Limerick, Ireland.
