Boundary-Scan Tools Keep Pace with Device Innovations

The boundary-scan technique, originally proposed in 1985 and promulgated as the IEEE 1149.1 standard in 1990,¹ employs a four-wire bus to pump test signals into and out of boundary-scan compatible devices through the test access port (TAP). Boundary scan is often referred to as “JTAG”, after the Joint Test Action Group that later became the original IEEE P1149.1 working group.

Boundary-scan considerations extend from product development through manufacture. To develop a scan-compatible board, you will need to specify boundary-scan-compatible components from firms like Altera, Intel, National Semiconductor, Texas Instruments, and Xilinx. At the manufacturing end, you will need a production ATE system such as Hewlett-Packard’s 3070 in-circuit board test system, GenRad’s GR228X production test system, or a Teradyne system running that firm’s Victory boundary-scan software.

One firm — Aehr Test Systems — has extended boundary-scan capability all the way to environmental test. It has adapted its MAX burn-in system so Texas Instruments can dynamically burn-in scan-compatible digital-signal-processing chips.

Between initial device selection and final burn-in, you will face a variety of challenges in developing successful boundary-scan boards. Fortunately, vendors are offering tools that help you meet those challenges.

From Design to Test

A variety of tools can help you span the gap from PCB design to production test. National Semiconductor, for example, offers Scan Ease software that supports automatic test-pattern generation. To ease the transition to production, Scan Ease is compatible with Teradyne’s Victory boundary-scan technology as well as with scan tools from JTAG Technologies.

JTAG Technologies in turn supports devices from various silicon manufacturers in addition to National Semiconductor. Its FlashBlaster device programmer — consisting of an ISA card, a TAP pod, and a SCSI-2 type interconnection cable — can program Intel flash memory devices through the boundary-scan port. The system’s four test access ports support shift frequencies from 100 kHz to 25 MHz in 100-kHz steps. FlashBlaster can program a 16-Mbit Intel 28F016 in less than 10 s at 25 MHz. JTAG Technologies supports other flash memory makers as well; its BFPG (Boundary-scan Flash Program Generator) supports 800 flash types. In addition, the firm supports Altera and Xilinx PLDs.

Goepel Electronic is another firm linking design to test. Its System Cascon software interfaces development data with test equipment such as the firm’s own PC-based and VXIbus-based test tools or production ATE systems from firms like HP, Teradyne, and GenRad. Cascon can import CAD/CAE files and automatically generate test programs and associated documentation.

In addition to systems spanning design to test, you also will find tools that help you focus on particular areas — from prototype debugging to device programming. Corelis, for example, introduced last summer its ScanPlus Debugger, a Windows 95/NT-based software and hardware package that helps pinpoint opens and shorts on and between fine-pitch scan-compatible BGA devices on prototype boards. The ScanPlus Debugger includes a pin browser (Figure 1) that allows you to view and select individual pins or groups of pins. You can enter and display signal data in binary, decimal, or hexadecimal formats, and you can save debug sessions.

Figure 1. A pin-browser graphical user interface on the Corelis ScanPlus Debugger assists in the development and debug of boundary-scan circuitry.

Boundary-Scan Development

When you develop a PCB populated by one or more scan devices, you need a convenient way to describe the device configuration to your test equipment. Usually, that’s done via a BSDL (boundary-scan description language) file, a device description provided by your silicon vendor and readable by your test equipment. With standard chips or custom or semicustom devices programmed by your silicon vendor, application of the BSDL information is relatively straightforward. If, however, you’re choosing programmable logic devices that you will program yourself, then the BSDL information provided by your PLD vendor may not yield an efficient test solution.

According to Acugen, that’s because the PLD vendor’s BSDL files represent an unprogrammed device and typically declare nearly all pins to be bidirectional. In your circuit, however, these pins may be connected to the drivers of nonscan devices, which cannot be disabled for in-circuit and scan testing. In addition, you may not use all available PLD pins and, hence, not provide test channels on your test fixture for unused pins.

Acugen suggests modifying the BSDL file to declare which pins are input-only or unused. To simplify what could be a tedious programming chore, requiring perhaps 3000 to 6000 keystrokes for a 200-pin FPGA, Acugen offers its PROG BSDL customiser package, which cuts the task down to fewer than 100 keystrokes (Figure 2).

Figure 2. Acugen’s PROGBSDL takes the vendors BSDL file for an unprogrammed device, combines it with your design files, and generates a custom BSDL output for use by your test equipment.

PROGBSDL software reads your PLD design files to determine how each pin is used. You can use a standard Acugen ATGEN constraint file to further restrict pin usage. Subsequently, PROGBSDL writes a new BSDL file with a modified boundary-scan register description reflecting the design-specific pin usage.

In-System Programming

ASSET InterTech, a Texas Instruments spin-off company, takes support for programmable devices a step further with its ISPExtender, an optional in-system-programming module for the firm’s PC- and VXI-bus based ScanDriver boundary-scan test system.

The ISPExtender supports SVF and Jam formats. SVF, the Serial Vector Format developed by Texas Instruments and Teradyne in 1991, is a standard ASCII format that expresses test patterns that represent the stimulus, expected response, and mask data for IEEE 1149.1-based tests.

The Jam programming and test language, developed at Altera and endorsed by several PLD vendors, programming equipment makers, and test equipment manufacturers in July 1997, is a standard file format designed to support programming and testing of PLDs via IEEE 1149.1 Test Access Port (Figure 4). You can freely licence the Jam language; most of the source code is available for download at Altera's Web site (www.altera.com) as well as a dedicated Jam Web site: www.jamisp.com/.

Figure 4. The Jam programming language consists of two components. The Jam Composer, generally written by a programmable logic vendor, writes a file that contains user data and the algorithm required to program a design into a device. The Jam Player reads the Jam file and applies programming and test vectors to devices via the four-signal IEEE 1149.1 Test Access Port, which includes TMS (Test Mode Select), TCK (Test Clock), TDI (Test Data In), and TDO (Test Data Out) signals.

A key goal of the Jam language is to cut device-programming file sizes. Small file sizes are important because vendors of products containing PLDs often provide field upgrades by shipping flash memory cards to their customers; the memory cards must contain the upgraded data as well as the programming algorithm. The Jam language employs data compression and high-level commands — including For-Next loops — to shrink the fully expanded code required to test and program a 128-macrocell device from a typical 20 MB down to 8 kB.

With ISPExtender’s support of boundary-scan test and in-circuit programming, ASSET InterTech aims to move boundary-scan test and in-system programming tasks from dedicated, expensive in-circuit testers onto the company’s lower cost PC- or VXIbus-based systems. ISPExtender also runs on DSP emulation hardware from Texas Instruments and White Mountain DSP.

Device Synthesis

If you are designing your own silicon, you will need to include boundary-scan test structures within your design. One tool that can help you do that is LogicVision’s icBIST, recently released as version 3.0. Designed to support at-speed testing of logic, embedded memories, and cores, icBIST can generate a complete IEEE 1149.1 boundary-scan implementation.

At the beginning of the design cycle, icBIST generates built-in self-test (BIST) design objects in the form of VHDL or Verilog RTL (register transfer level) code. The logicBIST and memBIST components provide functionality for testing logic, embedded memories, and cores.

The tapBIST portion creates RTL code for a complete IEEE 1149.1-compliant top-level module. It automatically generates a BSDL file for use at the board level. A TAP controller allows users to add their own instructions through a parametric instruction register.

SynTest’s TurboBSD also generates Verilog or VHDL RTL codes for boundary-scan structures. You can customise those RTL codes for synthesis using your own technology libraries, or you can have TurboBSD directly generate Verilog or VHDL cell-level netlists.

More than Interconnect Test

Boundary scan began as an attempt to verify board interconnect integrity. Today, the emphasis is shifting toward probing deeper into individual chips, which are increasingly comprising complete processor/memory/support-logic systems. The new emphasis is spurred on by engineers facing the prospect of testing gigahertz parts on ATE systems that max out at 450 MHz. For example, this year’s IEEE VLSI Test Symposium included several presentations on how to test devices whose speeds exceed those of available ATE.²

The boundary-scan concept is adapting to meet the requirements of fast, dense chips. IEEE 1149.1’s virtual nails that reach into hidden corners of BGA-packed PCBs are evolving into even smaller virtual nails that reach far into system-on-chip packages to test logic cores. These nails are being developed by the IEEE P1500 Working Group on Standards for Embedded Core Test.

IEEE 1149.1 boundary scan has itself been employed to exercise nonscan components embedded within a chip. Goepel Electronic, for instance, has demonstrated the use of the TAP to shift data into the input of a digital-to-analogue converter embedded within a mixed-signal chip. And LogicVision’s jtag-XLi technology can be used to implement logic cores that can be tested at rated speed via an IEEE 1149.1 test access port.

Considerable effort is taking place to develop consistent methods of testing high-speed systems on chips. In addition to the IEEE P1500 group, the Virtual Socket Interface Alliance is working to speed the development of de facto standards governing system-on-chip test. It is clear that although ATE speeds might lag device speeds, device vendors and users will continue to rely on test-equipment vendors to continue supplying the test patterns to (and monitoring the responses of) whatever built-in self-test structures emerge.

Footnotes

1. “IEEE 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE, Piscataway, NJ, USA. www.standards.ieee.org/catalog/test.html.

2. Proceedings, 16th IEEE VLSI Test Symposium, IEEE Computer Society, Los Alamitos, CA, USA. www.ieee.org.

For Further Reading

Goepel Electronic offers an on-line tutorial at www.goepel.com/english/prod/bsc/tutorial.htm.

The IEEE P1500 Working Group on Standards for Embedded Core Test maintains a Web site at grouper.ieee.org/groups/1500/index.html

National Semiconductor offers a scan-design home page with application notes, data sheets and BSDL source code for several devices: www.national.com/appinfo/milaero/SCAN/scanpage.html.

Texas Instruments offers a boundary-scan home page at www.ti.com/sc/docs/jtag/
jtaghome.htm. You can download an interactive boundary-scan tutorial from www.ti.com/sc/docs/jtag/educ.htm.