Flying Probe and Boundary Scan Testers Unite
Flying probe and boundary-scan ATEs can behave as a single tester that provides precise fault diagnosis on 98% throughput of complex boards.
Tamás Marosvölgyi, Siemens Test Engineering Competence Centre, Munich, Germany; Herbert Tietze, Itochu SysTech, Düsseldorf, Germany; Thomas Wenzel, Göpel Electronic, Jena, Germany -- Test & Measurement World, 8/1/1999
| Faced with the problem of raising the fault coverage on low-volume production of complex printed circuit boards (PCBs), engineers at Siemens Test Engineering Competence Centre devised a combined ATE strategy based on independent flying probe and boundary-scan tests systems. Essentially, the strategy combines and capitalizes on the complementary in-circuit test advantages of each system. The flying probe ATE excels on analogue tests; the boundary scan ATE excels on digital tests. The mutual compatibility of each ATE is inherent because both employ fixtureless test methods, which simplifies board handling, speeds up test program generation, and enjoys low support cost. Together, the ATE combination allows you to increase overall fault coverage without increasing overall test time. In fact, in the application described, the combined ATE produces a useful reduction in overall test time by allowing you to operate each ATE under its optimal conditions. Using the combined ATE strategy on a particular PCB unit-under-test (UUT) (see Figure 1), the Test Centre achieved complete diagnosis and fault identification on 98% of the volume of test throughput. In addition, the UUT includes some programmable devices, so the on-board programming facility of the boundary-scan tester is an added advantage.
As a further bonus, Test Centre engineers also raise fault coverage by using the boundary-scan tester’s programming feature to simulate hardware failures. They achieve this by programming temporary faults into special data registers implanted in the board’s ASIC/FPGA hardware. Not only does this technique extend general fault coverage, it also helps to identify even more faults to component or board level. Board Includes Non-Scan ICs
Although boundary-scan implementation seems fairly high at first sight, in fact the resulting testability using boundary scan alone is quite low. The problem arises in this design because the location of the non-boundary-scan ICs highly isolates the boundary-scan ICs. Table 1 shows a detailed distribution of the full-, partial, and non-boundary-scan devices. In total, the boundary-scan chain includes 2278 scan cells. Developing the Test Strategy AOI & BIST Play a Part For example, boundary scan can detect and diagnose pin-level faults only if a direct connection exists between at least one scannable driver and a scannable sensor. Also, minimising repeat checks, especially avoiding double checks at pin level, allows you to reduce the number of flying probe test steps. In this way, you can restrict the flying probe ATE to parametric tests and coverage of non-scannable pins. To test isolated boundary scan pins you can use the flying probes as virtual boundary scan pins. In this way, the test temporarily transforms isolated pins into fully testable boundary scan pins. Standard in-circuit testers with parallel pin electronics and bed-of-nails contacts already employ this principle. The advantage here is higher boundary-scan test speed and higher fault coverage compared to normal flying probe capability. Because the UUT in this application includes a microprocessor IC and programmable devices, the strategy can include BIST. The system loads the self-test into the programmable parts via boundary scan. Boundary scan can also read out test results at the completion of the overall test. Table 3 shows the final sequence of individual test steps and the time taken at each step. For comparison, the table includes a similar test sequence using only a flying probe ATE (with an opens check option). You can see that the combination ATEs execute more tests in less time and add in-circuit programming and BIST. Software Has Flying Probe Tool The software allows free batch run definition, which means each user can define individual test sequences. The software also provides testability analyses for different filter functions on nets that only the flying probe ATE can test. In practice, test times reduce roughly linearly in proportion to the depth of boundary scan implementation. Around 30% of boundary scan devices can achieve a test time reduction of 50% in some applications, although much depends on an individual application. The individual test steps, except for the built-in self-test, were generated almost entirely automatically by using CASCON-GALAXY boundary-scan software or Fabmaster computer-aided-manufacturing software. Looking Ahead References 2. Siemens Test Engineering Competence Centre, “Mit Test zum Erfolg aus elektro AUTOMATION”, 8/98. |















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