Boundary-Scan Test Triumphs Over Ground-Bounce
Boundary-scan creates, then solves, its own test problem.
Hans Peter Richter, Siemens, Germany and Norbert Münch, Göpel Electronic, Germany -- Test & Measurement World, 8/1/1997
Boundary scan is a very effective technique for testing high pin-count ASICs, particularly on complex multi-layer boards. But that test technique inherently requires the simultaneous switching of multiple pins on an ASIC. In fact, the number of pins that a boundary-scan test requires to switch simultaneously may far exceed the number that ever switch together when you operate the product normally. This multiple and synchronous switching, in turn, introduces to a fault condition called ground-bounce, which becomes increasingly prevalent as ASIC pin-counts continue to grow. Ground-bounce occurs when an IC’s internal ground plane voltage shifts from the board’s 0 V supply line. See "When the Ground Moves" below for an explanation of the ground-bounce phenomenon.We detected ground-bounce problems for the ASICs on our board (see the "Telecomms Board Under Test," below) despite these components meeting all their electrical specifications. Also, simulation tests verify the ASICs' behaviour under normal operation when typically 40 to 50% of outputs switch simultaneously. ASIC designers do not consider the possibility that all outputs might switch at the same time because of unrealistically higher costs. The difference in the number of pins that switch simultaneously in test mode compared with the number in normal operation determines the probability of malfunction due to ground-bounce. Therefore, especially high pin-count ASICs and FPGA/CPLD devices with integrated boundary-scan are especially prone to ground-bounce.
Typical Test Flow
A typical boundary-scan test flow (see Figure 1) used on our telecomms board includes a wide variety of test types:
• Infrastructure test to check the scan path and device ID
• Interconnect test to check for board opens and shorts
• Built-in self-test to confirm ASIC functionality
• Cluster test and dedicated memory test for non-boundary-scan devices
• On-board programming of flash memories
The most efficient way to create test vectors is to use the system’s automatic test pattern generation (ATPG) and diagnosis tools. Test programs you generate in this way contain the lowest number of test vectors and achieve the highest possible fault coverage. Using an ATPG is essential because a boundary-scan system shifts all test patterns in and out serially. Naturally, vectors optimised in this way are likely to contain multiple and simultaneous level changes. For example, the system makes stuck-at-low checks by means of drive-high vectors and stuck-at-high checks by means of drive-low vectors. Almost all component pins switch during the change between these checks and, in turn, increase the likelihood of ground-bounce.
Furthermore, boundary scan requires all register operations to strictly synchronise with the test bus clock (TCK) so that a test applies all new output vectors simultaneously. The combination of these two effects further induces ground-bounce problems.
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Test Problem Arises
During a boundary-scan test, a board malfunction leads to an interconnection test abort. The diagnosis message indicates a scan path interruption, although the infrastructure test previously executed did not detect a failure. The system executes all other procedures (see Figure 1) without faults.
Investigations reveal that a particular test vector reproduces the problem. At this vector in the test sequence the boundary-scan test logic switches from the test state to the normal mode. The reason for failure is a reset of the boundary-scan test access port (TAP) controller and this "false" reset arises from a ground-bounce pulse. This ground-bounce effect renders the overall test program meaningless.
Since an interconnection test is an indispensable part of an entire boundary-scan test strategy, you have to consider how to overcome the problem. There are several approaches:
• You can generate test programs manually;
• You can manually subdivide the board into sections and use several ATPG runs; or,
• You can persuade your test system vendor to build anti-ground-bounce features into the ATPG and diagnosis tool.
The first approach is time consuming and expensive. The second approach provides lower fault coverage because the system won’t detect faults between the subdivisions. The third approach is preferable because ground-bounce is a fundamental problem that will gain importance as ASIC complexity continues to increase. We adopted the third approach. The vendor took approximately three months to make the necessary changes to the tool, in the meantime production test proceeded using the second approach of subdividing test into smaller runs.
New ATPG Features
The improved ATPG tool now allows you to limit the number of pins that switch simultaneously at each test step. The limit only applies to ICs that potentially face ground-bounce problems. The test system treats all other ICs as before. A dialogue box allows you to enter ground-bounce parameters before an ATPG run. Because circuits with a high number of pins are more prone to ground-bounce problems, the new ATPG algorithm only applies to ICs with a pin number above your "critical pin count" setting (Reference 1).
The two-phase structure of the ATPG algorithm requires you to set two percentages. The first selection—"critical output switches"—contains the limited number of switches for the main phase of test vector generation. The second selection—"maximum output switches"—is the absolute limit that the algorithm must not exceed.
By adhering to these values, the test system ATPG avoids ground-bounce on switching from one drive vector to the next. The change from normal mode to test mode remains a critical time because usually you don’t know the state of the pins before switch-over. Therefore, you can select a test vector as a switching vector for which all pins are tri-stated or pins for which the boundary-scan cells acquire safe values. The corresponding boundary-scan description language (BSDL) data for the boundary-scan devices gives the safe values for the scan cells, although the system can partially overwrite these values for a particular board.
Table 1 shows the program settings for the board under test in our application and the corresponding test results. The table also compares test results before and after the addition of an anti-ground-bounce program. No ground-bounce occurs with the anti-ground-bounce program operating, and the number of test vectors increases only minimally so that test time does not exceed the settings.
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Hans Peter Richter is a production test engineer for telecommunications modules at Siemens’ Öffentliche Kommunikationsnetze, Bruchsal, Germany. Norbert Münch is head of software development for boundary-scan test at Göpel Electronic in Jena, Germany.
Reference
1. Göpel Electronic, User Manual Cascon Galaxy 4/1997.
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When the Ground Moves Because current flowing to ground depends upon IC operation, the chip’s internal ground level continuously fluctuates. If the internal ground plane voltage rises to core logic switching thresholds, then the likelihood of invalid logic behaviour arises. Current transients that occur as outputs toggle are especially insidious in this respect and also are difficult to reproduce. Short circuits between signal pins and high-signal lines or stuck-at-high faults pose yet another hazard. In practice, the number of ground-bounce defects is a manufacturing variable and, as a result, they are notoriously difficult to track down.
PC-Based System Telecomms Board Under Test
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