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Get to the bottom of stacked dice

Techniques let you preserve stacked chips for electrical tests and failure analysis.

Christopher C. Flores, Intel Technology Philippines, Cavite, Philippines -- Test & Measurement World, 2/1/2002

Figure 1. A cross section of an S-CSP shows the two memory chips, one mounted on top of the other.

The stacked-chip scale package (S-CSP) provides a way for IC manufacturers to stack two dice and mold them into a single package. At Intel, we have combined Flash memory and SRAM on a single substrate (Figure 1 ). During development, we found the bottom die often exhibited what we call "blown-up" failure, but the S-CSP configuration complicated failure analysis; it was difficult for an analyst to extract the bottom die without destroying it. Thus, we needed to devise an extraction technique that would leave the bottom die intact so we could repackage it for electrical testing and analysis.

With the technique we developed, we remove the upper die, remove adhesive and residual molding compound, and fasten the bottom die on a ceramic interposer—a small ceramic chip carrier package. Then, we rebond the free bottom die and locate and identify faults.

Isolating a die usually involves one of three methods: chemical, thermochemical, or mechanical. The chemical method involves soaking the partially decapsulated unit in a heated acid, such as nitric acid. (Partial decapsulation involves chemical removal of the molding compound used in the IC package.) The nitric acid dissolves adhesive between the two die to make them easy to separate. It also cleans off any adhesive sticking to the passivation surface of the bottom die.

In the thermochemical method, analysts heat the decapsulated package prior to treating it with acid. Heating for 20–30 min above the adhesive's glass temperature decomposes, or carbonizes, the organic components of the adhesive between the two die. This process makes the adhesive more susceptible to removal by an acid.

Unfortunately, due to the long etch times involved—30 to 45 min—the chemical and thermochemical methods do not preserve the integrity of the bond pads. Thus, these two methods are useful only when there's no need to run electrical tests on a die after the treatments.

Polishing preserves the die

The third option—mechanical isolation—involves grinding or cutting away unwanted material to provide access to a device. When done carefully, this method preserves the electrical functions of, and connections to, a die.

We needed to maintain the electrical integrity of the bottom SRAM die in our S-CSP, so we mechanically polished the S-CSP using fine planar lapping. In effect, we ground away the upper die a little at a time. We continued polishing until we reached the adhesive layer that had cemented the top die to the one below it. At that point, we removed any residual adhesive and molding compound with a quick acid etch of 2 to 3 min. This bottom-die recovery technique let us obtain the die without degrading or destroying its electronic characteristics.

In the polishing equipment, a specimen is attached to a mounting plate

Figure 2. After polishing away the upper die, some residual silicon and adhesive remained on top of the bottom SRAM die.
Figure 3. A quick acid etch of the SRAM die removed the adhesive and most of the silicon artifacts.
Figure 4. The quick acid etch revealed the gold balls, but it did not damage them. The gold balls provide connection points for wire bonding.
Figure 5. Placing the die—attached to a ceramic interposer—in an empty ceramic chip carrier made it easy to bond out electrical connections on the SRAM.
Figure 6. The image from a SEM shows damage on the SRAM caused by the sharp edges of the glass filler used in the die-to-die adhesive.
that holds it rigidly in place. In most cases, we would mount an S-CSP using the solder balls that would connect the package to a PCB. But to increase rigidity during polishing, we removed the solder balls so we could mount the entire bottom of the S-CSP to the polisher's mounting plate. The added rigidity let us more accurately control the polishing process. And removing the solder balls made it easier to attach the die to an interposer after processing. We attached the S-CSP to the mount using a thermoplastic adhesive. After polishing the S-CSP, we removed it by reheating the metal mount.

Grinding through the upper die down to the thin die-to-die adhesive layer required careful control of the polishing operations; factors such as the speed of the polishing wheel, the planarity of the lapping film on the polishing wheel, the orientation of the S-CSP with respect to the polishing film surface, and the grit size all contribute to the success of an operation. We removed the bulk of the molding compound by using 1-µm to 30-µm diamond lapping films. As soon as the polishing revealed some of the die-to-die adhesive, we switched to sub-micron diamond lapping films to avoid scratching the protective passivation layer of the bottom die.

We stopped polishing when we exposed more than 50% of the adhesive layer (Figure 2). Any silicon that remained from the top die usually resulted from a slight variation between the plane of the polishing wheel and the plane of the upper die. A small amount of remaining silicon does not affect access to the bottom die.

Clean up with acid etch

Chemical etching in hot fuming sulfuric acid cleaned the bottom die of residual mold material, adhesive, or silicon (Figure 3). If we had needed to remove only epoxy adhesive on top of the passivation layer, we could have used ethylenediamine (EDA) to delaminate the materials from one another. An etch time of a few minutes prevented gross corrosion of the bond pads and excessive etching of the substrate. (Over-etching the substrate material can loosen the die and make it unstable during mounting on the interposer.)

As we etched away the residual mold material and adhesive, we eventually uncovered the gold balls that connected the bonding wires to the die. Polishing had already ground away the bonding wires. The remaining gold balls allowed us to rebond new wires to the die (Figure 4).

We used double-sided adhesive tape to mount the polished sample on a ceramic interposer and then connected the gold balls on the die to the contacts on an empty ceramic chip carrier (Figure 5). This enabled us to electrically test the bottom die, and our tests showed the die drew excessive current.

Look for trouble

By examining the die through a microscope, we could see damage to the die's passivation layer at a point under the edge of the top Flash-memory die. After isolating the bottom die, we examined it with a scanning electron microscope (SEM). The resulting image showed a crater-like defect (Figure 6), probably caused by impact stress produced by a minute particle on the die's passivation surface.

When developing the S-CSP, we used two types of die-to-die adhesives: a polymer-filled epoxy and a glass-filled epoxy. Comparative analysis showed the failed units all used the epoxy containing angular glass filler; all of the units that included the polymer fillers—no sharp edges and corners—worked properly

We concluded that the hard, angular glass filler produced the crater-like damage on the passivation layer of the bottom die. As the top die was pressed into the glass-filled adhesive, sharp corners and edges in the filler concentrated stress at points on the passivation layer of the bottom die.

This type of defect exemplifies a failure due to packaging materials. Our analysis clearly showed the destructive interaction between the adhesive and the S-CSP bottom die. Without a technique that carefully uncovered the bottom die for both visual examination and electrical testing, we wouldn't have had an opportunity to determine the root cause of failures in the S-CSP memory products.













































For more information

Schaffer, James P., Ashok Saxena, and Stephen D. Antolovich, The Science and Design of Engineering Materials, Irwin Publishing, Toronto, ON, Canada, 1999.


Author Information
Christopher C. Flores works as a package failure-analysis engineer at Intel Technology Philippines. Most of his failure-analysis works involves Flash memory and flip-chip packages. He obtained his bachelor's degree in Metallurgical Engineering from Mapua Institute of Technology (Intramuros, Manila, Philippines).


Acknowledgement
Information in this article was included in "Failure Analysis of Stacked-Chip Scale Package," ISTFA 2000: International Symposium for Testing and Failure Analysis, ASM International, Materials Park, OH, November 2000. Used with permission.

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