IEEE 1149.1 yields new standards

The IEEE 1149.1 boundary-scan standard, developed more than 10 years ago to test otherwise untestable PCBs, has been pressed into service to perform a variety of functions that weren't clearly envisioned by its developers back in 1990. Recent efforts are resulting in new standards that build on IEEE 1149.1 to provide device test and programming capabilities. The 1149.4 standard (which adapted boundary-scan technology for analog components), the 1532 standard (which implements boundary scan in silicon for PLD programming), and the draft P1500 and P1581 standards (which cover test structures for systems-on-chips and memory devices) all promise to provide better access to circuit-board components.

Figure 1. With test mode selected, scan cells within ICs become virtual test points. Here, a boundary-scan system can drive logic signals into virtual test point 1 and observe the results at virtual test point 2. If the results match, then the system has verified continuity from Device A through solder balls and PCB trace to Device B.

Virtual test points are actually boundary-scan cells that each consist of one or two latches. The latches store the logic state applied to the driving test point or capture the logic state at the observation test point.

Boundary-scan cells on all components in a design are connected serially to form a shift register, which is commonly called a boundary-scan chain. The ends of the chain connect to special pins designated as Test Data In (TDI) and Test Data Out (TDO). A pin called Test Mode Select (TMS) begins the process of shifting data into and out of a device; a pin called Test Clock (TCK) performs synchronization. A fifth, optional, pin called Test Logic Reset (TRST) returns control logic to a known state. These signals, along with an internal state machine, make up the Test Access Port (TAP) built into all IEEE 1149.1-compliant devices.

Figure 2. Test data flowing in a chip from the TDI to TDO pins normally traverses a device’s scan chain (whose individual scan cells are shown in yellow here). But test data can also serve as instructions that can be loaded into any internal register or to registers of non-scan-compliant neighboring chips.

Boundary scan can add value during all stages of a product's life cycle, beginning in development, where a PC-based boundary-scan tester can be used to verify prototypes. The boundary-scan TAP provides access to the on-chip debugging (OCD) features that vendors build into processors and microcontrollers. Once the project moves into production, a PC-based boundary-scan tester can function as a cost-effective method of verifying PCB assembly and of programming onboard flash memories, and it can perform in-system configuration of PLDs. After the product reaches the field, boundary-scan is an invaluable tool for running on-site diagnostics, for loading system updates from a portable PC, or for loading updates through remote access via a modem or the Internet.

Today, flash memory is rapidly moving into smaller packages where device handling and off-board programming become difficult. Putting sockets on a production board simply isn't practical. And the sockets on high-volume programming stations will last for only a few thousand insertions, sometimes requiring replacement every day. Just-in-time off-board programming can resolve some inventory-management problems, but handling these fragile devices twice—once for programming and once for board placement—leads to increased assembly-test fallout and expensive board rework. In addition, without onboard programming, a board is frozen in one configuration after its assembly. To reconfigure a board, you would have to remove the flash devices to reprogram them, which would very likely destroy them.

Onboard programming of flash memories allows boards to be assembled with blank devices. Once a board has been assembled, a single system performing both test and programming chores can load data either by using the IEEE 1149.1 TAP interface to a processor with access to the flash memory or by using the boundary-scan registers of adjacent IEEE 1149.1-compliant devices. The latter option avoids reliance on a processor and its emulation tools for programming.

The simplest way for boundary scan to access flash memory is to place address and data information on the appropriate inputs and toggle the control signals. A boundary-scan programming tool can wait for the write cycle to complete either by reading the device's flash status register or by monitoring its Ready/Busy (RDY/BSY) pin to determine when the programming operation has finished.

Figure 3 shows how a PC-based boundary-scan tool can program flash memory in a cell phone. Data and address information is accessible through the boundary-scan registers of an adjacent device, while non-scan signals provide access to control signals. Using non-scan signals here reduces the number of scan operations required by the programming process, decreasing programming time by 50% or more.

Figure 3. Under PC control, a boundary-scan tool can program flash memory in a cell phone. A boundary-scan device adjacent to the flash memory acts as a highway for the programming data.

PLDs, as well as flash devices, can benefit from in-system programming for the same reasons: quick reconfiguration of devices during design debug, elimination of sockets, reduction in the number of times fragile devices must be handled, simplification of inventory management, and easy reconfiguration in the field. Yet the in-system configuration (ISC) of logic differs from the in-system programming of flash memory.

Unlike flash programming, where an adjacent boundary-scan device controls the process, most CPLDs and FPGAs have boundary-scan cells on chip. PLDs are programmed with special instructions that select internal programming registers that are loaded with the address and data information. Once the programming operation is initiated, the TAP state controller goes into a wait state during the PLD burn time. When complete, the controlling software moves to the next location to be programmed, and the process is repeated.

In 1992, Lattice Semiconductor (www.latticesemiconductor.com) introduced the concept of in-system programming (ISP) with a proprietary serial-access method. Other vendors quickly followed with their own methodologies. Vendors such as Vantis (now part of Lattice), Altera (www.altera.com), and Xilinx (www.xilinx.com) noted the trends toward using boundary-scan test and ISC and converged the two to take advantage of the boundary-scan architecture and to provide a standards-based method for programming via serial access (Ref. 1).

In 1997, several companies formed a Working Group to standardize the methods for in-system configuration so tools could be developed to support PLDs from all compliant vendors. The group was also charged with developing a way to simultaneously program devices from different vendors. The Working Group consisted of representatives from the PLD industry including Xilinx, Altera, Lattice, and Atmel (www.atmel.com), from in-circuit test vendors like Agilent Technologies (www.agilent.com) and Teradyne (www.teradyne.com), and also from the PC-based boundary-scan test industry such as ASSET InterTech (www.asset-intertech.com), Corelis (www.corelis.com), Intellitech (www.intellitech.com), and JTAG Technologies (www.jtag.com).

One of the first decisions of the Working Group was to require that PLDs conforming to the new standard conform to the existing IEEE 1149.1 boundary-scan standard as well. This decision enabled vendors to reuse much of the logic already placed in most CPLDs and FPGAs, and they could make use of the boundary-scan tools that supported these devices. In 1998, the Working Group applied to IEEE for sanctioning, and in 1999 the IEEE P1532 Working Group was established.

In September 2000, the IEEE 1532 standard (Ref. 2) for in-system configuration of programmable devices was officially accepted by the IEEE. The first version defines the requirements for implementing the standard in silicon. Work on the standard has continued, and the second version, which defines the software that is used by tools to program devices in-system, was adopted in December 2001. IEEE 1532's software portion defines the extensions to the Boundary-Scan Description Language (BSDL) format needed to describe a device's programming algorithm, as well as a programming data format designed for use with boundary scan.

The 1532 committee also tackled the issue of programming multiple logic devices from different vendors concurrently. When several PLDs are programmed concurrently, all the devices enter and leave the programming wait state at the same time. Because access to the devices via IEEE 1149.1 is quick, the time the devices spend in the wait state, or the burn time, is the most significant contributor to the total programming time. Programming devices concurrently instead of sequentially cuts the total programming time significantly. The Working Group is currently completing several studies to quantify these time savings.

Another IEEE standard that builds on the IEEE 1149.1 boundary-scan standard is the IEEE 1149.4 standard (Ref. 3) for a mixed-signal test bus. The IEEE 1149.1 standard was developed for use with digital signals, but few circuit boards are solely digital. Analog components face the same miniaturization pressures that digital circuits do. In fact, some analog components, such as discrete capacitors and resistors, are being designed into the laminate substrate of circuit boards. In such cases, physical access and visual inspection are impossible. The IEEE 1149.4 standard addresses some of the basic requirements for providing virtual access for mixed-signal test.

First, IEEE 1149.4 requires that compliant devices conform to IEEE 1149.1, providing digital access to all pins. But pins functionally designed for use with analog signals and the external circuits they connect to do not often lend themselves to digital tests. For example, termination resistors and in-line capacitors can appear as shorts or opens to a digital signal. To make virtual analog testing possible, the IEEE 1149.4 standard defines two additional test signals, AT1 and AT2, which can internally connect to any pin in an IEEE 1149.4-compliant device through an on-chip switching matrix. These signals either provide an analog stimulus to a pin or observe the analog response on a pin. By connecting an external signal source to one pin and an external measurement device to the other, you can determine the actual value of analog components (Ref 4).

Although the IEEE 1149.4 standard was approved in 1999, semiconductor makers have been slow to provide compliant devices; they've been waiting for their customers' threshold of pain to reach a point where they demand such devices. Several successful feasibility studies have been done, most recently by Lockheed Martin Space Systems (www.lockheedmartin.com) using a general-purpose device developed by National Semiconductor (www.national.com) in conjunction with LogicVision (www.logicvision.com). The device features nine 1149.1-controlled analog test points in addition to four low-impedance CMOS switches that can be configured into a variety of analog multiplexers and demultiplexers (Ref. 5). For the feasibility study, access to the IEEE 1149.1 boundary-scan chain and IEEE 1149.4 features was provided by ASSET InterTech's ScanWorks boundary-scan environment. A visual display of the layout and schematics along with access to design information was provided by OHIO Design Automation's (www.ohio-da.com) InterComm design browser, which has been integrated into ScanWorks.

Most general-purpose processors already use the boundary-scan TAP for emulation or debug (Ref. 6), including those from IBM (www.ibm.com), Intel (www.intel.com), and Motorola (www.motorola.com), as well as most digital signal processors (DSPs) from Analog Devices (www.analog.com), Lucent (www.lucent.com), and Texas Instruments (www.ti.com).

Practically all processor vendors and a host of third-party tool suppliers, such as Wind River (www.windriver.com) and Applied Microsystems, provide in-circuit emulation and development tools that are based on the 1149.1 standard and are used for embedded software development.

Another boundary-scan-based standard, the Global Embedded Processor Debug Interface Standard (GEPDIS), has been approved by the IEEE Industry Standard and Technology Organization (www.ieee-isto.org) for in-circuit emulation of microcontrollers, mostly in automotive applications. GEPDIS was drafted by the Nexus 5001 Forum (www.nexus5001.org), and the standard is now known as the IEEE-ISTO 5001 standard.

The standard calls for the 1149.1 interface to validate the design of automotive RISC-based microcontrollers and system-on-chip (SOC) devices in real-time engine and vehicle control systems. In these applications, the standard augments the interface with one or several optional auxiliary parallel access ports for monitoring the real-time execution of RISC code. The boundary-scan TAP controls these auxiliary ports.

Static Component Interconnection Test Technology (SCITT) defines test structures that can be designed into memory devices so you can test them on a board through connections to adjacent boundary-scan-complaint devices (Ref. 7). SCITT development was begun by Philips Research (www.philips.com). A feasibility study proved the viability of the concepts using SDRAM and FCRAM (fast-cycle RAM) devices provided by Fujitsu (www.fujitsu.com). An IEEE Working Group (IEEE P1581) has been formed to create an IEEE standard to codify SCITT.

With SCITT, memory devices have an internal test structure that bypasses the device's functional circuits and connects input pins to output pins through a network of XOR gates, XNOR gates, or both. By following a set of rules for implementing this XOR/XNOR network, full fault detection and full single-fault diagnostics can be achieved with a small vector set (Ref. 8).

The SCITT memory devices used in the feasibility study enter the test mode at power up. The Working Group is considering other methods for initiating the test mode, such as a dedicated test-mode pin. Once in test mode, all outputs are an XOR/XNOR of a set of inputs, and all inputs are used in one or more of the XOR/XNORs.

The current draft of the preliminary P1581 standard recommends that the device be accessible via an adjacent boundary-scan device. The boundary-scan register of the adjacent device or devices stimulates and observes the pins on the SCITT device. The standard set of test patterns that can be applied through the SCITT devices consists of well-known serial scan patterns, including "all zeros," "walking ones," "all ones," and "walking zeros."

Most boundary-scan tools should be able to implement SCITT easily. When SCITT-complaint devices become more readily available, the effectiveness of testing interconnects to complex memory devices such as Rambus, SDRAM, and flash will further increase the usefulness of IEEE 1149.1-compliant components and the tools that support them.

With the emergence of SOC technology, built-in self-test (BIST) has taken on new importance. Because of higher device and board density, functional test—especially through a serial interface such as IEEE 1149.1—is becoming impractical because of the large number of test vectors required. In addition, IEEE 1149.1 provides only static testing, which often is insufficient for high-speed designs. BIST allows devices or boards to be tested at system clock speeds, resulting in the completion of tests in a fraction of the time needed for serial tests.

BIST makes use of the boundary-scan TAP to access internal test structures. The internal test structures can be designed to test a DUT's core logic or to test functional logic surrounding the DUT. Several companies, including LogicVision and Mentor Graphics (www.mentor.com), have developed tools that help you embed design-specific test structures into devices and boards. Certain common functions such as memory testing can be easily synthesized into a custom ASIC or an FPGA. When an OEM intends to program logic devices such as FPGAs using in-system programming via boundary-scan, embedded BIST structures can be loaded into the FPGA for board assembly testing; then, the system can be reprogrammed for functional operations just before it is shipped.

The IEEE P1500 embedded-core test standard (Ref. 9) is defining a core wrapper to provide access to test structures in embedded cores in SOC designs. The P1500 group is strongly considering a requirement that would make the wrapper accessible by IEEE 1149.1 boundary scan, but this has not been formally adopted (Ref. 10).

The AC EXTEST Working Group (Ref. 11), initially sponsored by Agilent Technologies and Cisco Systems, is working on a solution for testing AC-coupled nets that connect ICs on one or more PCBs. This group has been sanctioned by the IEEE as the 1149.6 Working Group. Traditionally, such interconnects have been DC-coupled and could be tested with well-known boundary-scan methods using the EXTEST command specified in IEEE 1149.1. But high-speed gigabit technology requires AC coupling between integrated circuits, and DC-based boundary-scan techniques cannot be used with AC coupling.

The Working Group is working on a proposal that would extend the capabilities of IEEE 1149.1 while maintaining a maximum level of backward compatibility with 1149.1 and 1149.4, enhancing the value of the 1149.1 infrastructure in the industry.