Compare aperture delay between ADCs
Captured FFT data can help you determine the aperture-delay variation of a DUT relative to a control unit.
Rob Reeder, Analog Devices, Greensboro, NC -- Test & Measurement World, 5/1/2002
If ADC aperture delay is important to your communications or data-acquisition applications, you must measure it. The spec might appear on an ADC data sheet, but most manufacturers list only typical values—not worst case. In phase-sensitive systems having multiple converters, you need a measurement method that extracts aperture delay data for each DUT, because calibration and alignment schemes depend upon it.
My colleagues and I have developed a repeatable test method that employs captured FFT data to determine the aperture-delay matching between a DUT and a control unit. The setup includes two evaluation boards that share a common sampling clock and input-signal source. A computer uses two synchronized data-capture boards to sample the outputs of the ADCs. We use a MathCAD (Ref. 1) program to analyze the collected data.
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| Figure 1. Effective aperture delay (te) is the time offset between when the ADC is asked to sample and when the sampling actually takes place. |
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| Figure 2. Aperture jitter is the sample-to-sample variation in aperture delay. |
Aperture delay (Ref. 2) is the time required, after assertion of a hold command, for the sampling switch to fully open in an ADC's sample-and-hold amplifier (SHA). This is the time from the edge of the conversion clock—when the ADC is asked to take a sample—to when the sampling actually takes place. Effective aperture delay (te) includes the aperture delay plus the effects of the analog and digital propagation delays within the SHA, and it can be positive or negative. Figure 1 shows how the sampling clock can be advanced or retarded to account for the effective aperture delay.Aperture jitter
Aperture jitter, or aperture uncertainty, is the sample-to-sample variation in aperture delay; it results from noise that modulates the phase of the system clocks. You can calculate aperture jitter by applying a root-sum-square (RSS) algorithm to the internal ADC clock jitter and the external sampling-clock jitter. For the measurement to be accurate, it is critical that the clocks in a sampled data system have very low phase noise. As the analog input slew rate (dV/dt) increases, the effect of aperture jitter also increases. Typically, the clock jitter should be in the subpicosecond range when using ADCs with input frequencies in the megahertz range. Figure 2 shows the results of aperture jitter.
Current aperture-delay measurement methodsTraditionally, you would use a clock source triggered from an analog signal source to measure aperture delay; you would use the clock source's offset adjustment to "move" the sampling clock while observing the effect on an oscilloscope. Specifically, you would first adjust the sampling clock until the ADC output is equal to midscale plus its inherent offset. (In a 12-bit converter, for example, midscale is decimal 2048.) Second, you would measure the difference between the 50% edges found on the oscilloscope channels for the analog input and the sampling clock. This is often a tedious task, even for just for one measurement. It is not repeatable because of the limited ability of the oscilloscope to make subnanosecond measurements and because of your limited ability to "eyeball" the measurements the scope makes.
Also, unless the setup is superbly matched, reflections would inhibit the accuracy of the measurement. Probes can introduce additional error and loading problems, so you would have to use FET probes, as they present a lighter capacitive load to the circuit. Also, you would need to swap the probes and repeat the measurement to account for any errors introduced by the probes themselves. Finally, the trigger cable would have to be a certain length (which would vary depending on the test setup and the analog input and sampling clock frequencies that you have chosen for the system) in order for this test to work.
Most test platforms measure ADC performance using some kind of computer-based sampling data-acquisition system that employs programs such as LabView or Visual Basic or custom in-house software. Frequency analysis using the fast Fourier transform (FFT) is the primary tool used to evaluate the ac characteristics of ADCs.
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| Figure 3. Measuring phase between two signals in the time domain is straightforward. |
è = (td/T) x 360° (1)
or
td= (è* T) / 360° (2)
where
è = phase in degrees
T = period in seconds
td= t1–t2, or the time difference (aperture delay) in seconds
New aperture-delay measurement methodIn the test method we have developed, you can find aperture delay after extracting the phase portion of each of the FFT data sets. The period, T, is 1/fa, where fa is the analog input frequency chosen for the test. Plug the delta phase (Äè) value into Equation 2 to find aperture delay (td). The result is the measurement of aperture-delay difference between two independent ADCs.
Remember that aperture delay is simply the time difference between the edge of the sampling clock and the point at which the analog input is actually sampled. The internal logic and analog-input path-delay differences of the ADC have nonzero values. The aperture delay is therefore related to the difference between the phase of the analog input signal and the phase of the converted spectrum.
In our test method, we employed two ADCs, one as the reference ADC and the second as the DUT. We soldered the reference ADC to one evaluation board; we installed a socket on the other board, allowing easy removal of the test ADC. Figure 4 shows the test setup, which uses the same clock and signal sources for both converter evaluation boards.
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| Figure 4. This aperture-delay test setup employs two evaluation boards: one with a control (reference) device soldered down and another that includes a socket to accommodate test of multiple devices. |
The test setup has short matched cable and connector lengths for both the clock and signal inputs. We removed all sampling-clock driver circuits on the evaluation boards. The data-capture boards are capable of 2n bits and are identical for both the control device and the DUT. Note that some of the data-capture lines connect together to capture the data simultaneously. These connections may vary depending on the data-capture system. The system must capture data on the same clock edge for each ADC so that each ADC's data is sampled concurrently.
Defining the softwareOnce the FFT data-capture software has captured two data sets onto the computer, the numerical analysis can proceed. The FFT routine in MathCAD provides an easy way in which to compare the two data sets. Figures 5a and 5b show 512-point FFTs generated from the imported data files of both the control ADC (data set A) and the DUT (data set B).
Equation 3 shows the delta phase between the two data sets:
(3)
Figure 5c shows the result.
To calculate the aperture-delay variation, substitute the appropriate variables from equation 2 into equation 3:
(4)
Figure 5d provides a visual display of the delay, point by point, between the two data sets. Our interest, however, is only at the fundamental test frequency. From Figure 5e, which shows the expanded magnitude plot of the fundamental peak, you can see that the peak point lies at 474. Now, taking the value of point 474 on Figure 5d or using Eq. 4, the resulting difference in aperture delays is 136.5 ps.
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| Figure 5. A MathCAD routine compares control and DUT sample sets, including (a) FFT magnitude and (b) phase, with red representing data set A (for the control device) and blue representing data set B (for the DUT). With that information, the routine derives (c) phase difference and (d) aperture delay. Zooming in on the FFT magnitude plot helps to locate (e) the fundamental peak. Using that peak point found in (e) yields the aperture-delay result (e.g., Delay474 = 136.5 ps). |
Figure 6 shows the distribution of five parts' aperture delay over variations in power supply and temperature. This test incorporated a 12-bit, 65-Msample/s ADC. Both power supplies, +5-V analog and +3.3-V digital, were varied in unison at –5% (green) and +5% (red) from nominal (blue). Temperature was varied from –10°C to +70°C. The maximum delta found within this group over supply and temperature variation is approximately 140 ps.
Figure 6. Power-supply and temperature variations resulted in the DUT characteristics plotted here.
Depending on the number of parts needed for characterization, these tests can be time consuming if done manually. Testing over temperature extremes and supply variation requires an automated process.
We have found our test method to be accurate and repeatable. Several data captures of the same part under the same test conditions yielded results that were repeatable to within ±3 ps. This uncertainty is a result of parasitic contacts that are recreated during each measurement, because the DUT was powered down and reinserted into the socket each time. Efforts to increase resolution using longer FFTs, however, have not proven successful.
Measuring delay variations from lot-to-lot and channel-to-channel is especially useful where phase information is important in multichannel systems in which the reference unit and signal paths are calibrated. This test method can be applied to many applications, including I/Q modulation, simultaneous-update memory-buffering ("ping-ponging"), and phase-array antennas, all of which involve multiple channels in which tracking between two or more ADCs is required.
| References |
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| For further reading |
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Kester, Walt, High Speed Design Techniques, Chapters 4 and 5, Analog Devices, Norwood, MA, 1996. |
| Author Information |
| Rob Reeder is a senior design engineer at Analog Devices' Multi-Chip Products Group, Greensboro, NC. He holds an MSEE degree from Northern Illinois University. For the past four years, he has worked in both the test and design arenas, developing high-speed ADC and DAC multichip modules for military, aerospace, and other high-reliability applications. |
| Acknowledgements | ||
| The author would like to thank Joe Bergeron, who wrote the initial MathCAD software definition, as well as Randy Carver, Mike Lewis, and Walt Kester, who offered their guidance and technical expertise. | ||
