Serdes devices challenge ATE

High-speed data-communications requirements are spurring on the development of gigabit-rate serializer/deserializer (Serdes) chips that can send and receive parallel data over a serial link. Like most new technologies, Serdes devices place severe demands on automated test equipment. In this case, ATE often lacks the internal clock rates necessary to exercise Serdes devices at rated speeds. Nevertheless, ATE vendors are developing techniques that support high-throughput tests of Serdes devices.

Serdes devices find use in data-communications applications conforming to a plethora of standards, ranging from chip-to-chip and board-to-board standards such as XAUI to long-haul telecommunications standards including SONET. Ken Lanier, senior marketing director at LTX, says that the application of Serdes technology to high-end processor communications schemes such as RapidIO (see "Serdes: U ART a long way from RS-232, baby," p. 20) will spur on high-volume Serdes production that will increasingly require a combination of datacom, RF, and VLSI-logic test capability. Each such serial-I/O standard specifies high-speed serial data transfer, and each relies on core Serdes functionality to condition data for high-speed serial transmission.

Figure 1 shows the basic components of a Serdes transceiver. In the transmit portion of the device, a data-input buffer accepts parallel data, 8 bits wide in this case. In Figure 1, a data encoder converts the 8-bit-wide data into a 10-bit-wide configuration. The encoding process, which is not mandatory, helps to ensure there are sufficient zero crossings in the serial data stream to facilitate clock and data recovery in the receiver and to serve for error checking.

Figure 1. Shown here in a loopback configuration, a Serdes device adapts parallel data for high-speed serial transmission. A clock-and-data-recovery (CDR) circuit and alignment FIFO buffer provide synchronization in the receiver.

A serializer converts the 10-bit-wide parallel data into a serial stream, which provides an input to a serial line driver, which in turn transmits the serial stream over a few inches of PCB trace or over many miles of telecommunications optical infrastructure. Most gigabit-rate serial drivers employ low-voltage differential signaling (LVDS), in which a few hundred millivolt swing on a differential pair, or data lane, represents the data. LVDS techniques save on power and reject common-mode noise.

At the receiver portion of the Serdes device, a deserializer together with clock-and-data-recovery (CDR) circuitry reconstructs the transmitted 10-bit-wide encoded parallel data (assuming the transmit portion includes the optional 8-bit/10-bit encoder). The CDR function is necessary because receiver and transmitter operate asynchronously, and both data and clock information are present in the received bit stream. A decoder restores the original 8-bit-wide parallel data, and an alignment FIFO buffer synchronizes the received data with the receiver's system clock.

Traditionally, the Serdes function itself has fully occupied a silicon chip, with network and protocol functions allocated to separate chips. As higher levels of integration become available, though, chip designers are combining the Serdes function with other circuitry into systems-on-chip (SOCs). Such chips present the gamut of test challenges to test engineers: the high pin count requirements typical of SOCs as well as the high-speed mixed-signal test demands of the Serdes cores themselves.

Although Serdes devices implement a purely digital function—serial data communications—they behave in an analog-like fashion, especially in the low-voltage differential signaling used at 10-Gbits/s speeds. Testing them requires making all the eye-diagram measurements, including minimum and maximum signal levels and rise and fall times.

According to Markus Knoch, application consultant for wired communications at Agilent Technologies, an SOC combining Serdes and networking functions easily can have 800 pins, and signal integrity issues can arise when logic circuitry not part of the Serdes core interferes with Serdes functions or when multiple Serdes channels suffer from crosstalk.

The ultimate figure of merit for a Serdes device is bit error rate (BER), explains Lanier. Most standards allow no more than one bad bit in 10¹². Unfortunately, says Tim Lyons, Serdes application manager at Teradyne, such tests using traditional BER measurement approaches require tens of minutes. While tests of this length are tolerable for low-volume Serdes-based parts selling at $5000 each, Lyons says that it simply isn't for a high-volume production-test environment that's cranking out thousands of low-cost devices. He does point out that sufficiently intelligent test systems can derive BER performance from jitter measurements, which can be extracted from eye-diagram measurements.

Toshifumi Watanabe, an applications engineer at Advantest, lists the key tests for Serdes devices:

• transmitter data jitter,
• transmitter eye opening,
• transmitter edge rise and fall time,
• receiver recovered clock jitter,
• receiver jitter tolerance,
• receiver bit-error-rate performance in response to pseudorandom bit-sequence test data, and
• receiver sensitivity (minimum input swings the receiver will recognize as valid data).

As this list suggests, jitter measurement is a key factor in Serdes test. But although jitter measurements provide a conceptually simple way to make BER tests, the implementation is difficult at the speeds of today's Serdes devices. Measuring jitter, signal levels, and rise and fall times requires the test system to source and measure the signals specified in the target standard. Today, high-end testers' pin electronics cards top out at the low gigahertz rates, far short of the 10-Gbits/s rates required for 10-Gbits/s Ethernet and OC192 SONET or the 40-Gbits/s rates that OC768 demands.

According to Rob Mosher, Teradyne's product manager for mass-storage/datacom test, Teradyne's approach to Serdes test is "applicate and integrate." The first stage involves custom setups of instrumentation and device-interface-board (load-board) circuitry to meet test requirements that demand speeds and other test capabilities that integrated pin electronics can't meet. The second involves integrating full Serdes test capability within the test-head pin electronics. Teradyne now offers its integrated Serdes test capability at rates to 3.2 Gbits/s; it introduced its 3.2-Gbits/s Serdes Port Qualifier (SPQ) pin cards for its Catalyst Tiger ATE system last October. Beyond 3.2 Gbits/s, Teradyne, and its competitors, employ tailored approaches.

Denise Schang, product manager for datacom test at Schlumberger, provides more detail on what integrated and tailored custom approaches look like. Schlumberger's approach for 3.2-Gbits/s and slower devices involves pin electronics that route 3.2-Gbits/s signals to and from the DUT; the pin electronics also connect timing interval analyzers from companies including GuideTech and Wavecrest and oscilloscopes from companies like Tektronix to the DUT for accurate jitter measurements. Such connections provide a simple physical interface to the DUT while minimizing load-board components, and they place control of all instrumentation within a single software environment.

For DUTs operating at more than 3.2 Gbits/s, Schang says that one approach for testing a Serdes receiver is to employ a "golden reference" transmitter—a device that's accurately characterized in a laboratory using benchtop or rack-and-stack instruments—on the load board. In such a test, a pin-electronics source card provides parallel data to the transmit section of a golden reference. The golden reference in turn generates a 10-Gbits/s differential serial signal that drives the receive section of the DUT. A pin-electronics measurement card measures DC parameters; external oscilloscopes and timing interval analyzers connected directly to the load board make AC measurements—specifically, they measure eye-diagram parameters and jitter. Similarly, a golden transmitter can serve in receiver tests.

Such golden components can be critical for test of very high-speed devices, but Agilent's Knoch recommends avoiding active devices on a load board whenever possible. Active devices on a load board can increase the load board's cost and can cause calibration and signal-degradation problems. Agilent has investigated an approach that employs only passive components on a load board to provide jitter injection tests. Those tests require adding jitter to the serial data stream to determine how well a receiver tolerates jitter on its input (Ref. 1).

Figure 2. Jitter measurements can be derived from eye diagrams, with these versions showing a transmitter’s jitter performance (a) without and (b) with transmitter-clock filtering. Test-system computations can derive rms jitter values from the histograms (shown in red). Courtesy of Schlumberger.

To accurately relate jitter to BER, a test system must separate two jitter components: random jitter and deterministic jitter (Ref. 2). The latter is independent of time and number of samples in a histogram; it stems from interference caused by switching power supplies or other digital circuitry, from crosstalk with other communications channels on a single chip, or from reflections caused by impedance mismatches. Random jitter stems from background shot noise within semiconductor materials, from 1/f noise, and from thermal noise. It is dependent on the number of samples, with peak-to-peak levels increasing over time.

Unlike deterministic jitter, random jitter is Gaussian in nature, with tails extending to infinity at each end of the Gaussian distrubution's familiar bell-shaped curve. It's the number of samples that fall at the extremes of such curves (beyond 14σ for 10^-12 error rates) that correlate accurately to BER specs, so it's important that an algorithm calculate these without being influenced by deterministic jitter components. Wavecrest employs a patented algorithm, called the TailFit algorithm, to make such calculations in its timing interval analyzers.

In addition to measuring jitter, a Serdes test system must also deal with data-alignment problems. Typically, a digital IC tester operates in a synchronous mode; it applies a test pattern and expects to see the appropriate response vector on the subsequent clock cycle. Serdes receivers and transmitters, however, operate asynchronously. Receiver and transmitter system clocks must operate within tolerances specified by the communications standard to which they conform, but they are not locked.

Agilent's Knoch points out that a test suite must involve detuning of a transmitter's clock within the range allowed by the standard to ensure that the receiver can successfully accommodate the difference between the detuned value and the nominal value, which it attempts to do by means of its data-alignment FIFO buffer. But the tester itself must also be able to accommodate the difference. To do that, the tester must have software that can examine the FIFO buffer outputs to determine and compensate for any offset in the received data.

Serdes devices are incorporating several design-for-test (DFT) techniques that help offload ATE systems. Many include IEEE 1149.1 ports through which DFT functions are initiated. Advantest's Watanabe cites internal loopback capabilities and simple BER tests employing pseudo-random bit-sequence generators as examples of Serdes DFT functions. Such simple tests can occur at the wafer level, with functional tests deferred to package test.

It's not always possible to defer functional tests until the package-test stage, though. LTX's Lanier notes that vendors of known-good die must provide complete functional test at the wafer stage—a process that's made more complicated, he says, by the fact that it's easier to make good RF contact with a DUT at the package level.

Knoch says some companies are working on jitter-injection DFT approaches as well as on internal eye-measurement capabilities. He suggests that internal idle-character generators could help to free ATE from the time-consuming post processing necessary to compensate for the pattern-alignment problems that stem from Serdes devices' asynchronous operation.

Teradyne's Lyons, though, cautions that Serdes DFT-derived results can be unreliable because Serdes devices push the limits of process variability. Lanier adds that implementing DFT at the high-speed side of a device "introduces the age-old problem of performance degradation due to the added circuitry. Given that many of these devices have very little performance margin, it is problematic to cause even a small reduction in performance. As with most new technology, more DFT and BIST will emerge once the failure mechanisms and process dependencies of the devices are better known. For now, functional and parametric testing is generally required to make end-users comfortable that these devices are performing to spec."

It's true that an individual chip's DFT structures aren't amenable to the accurate characterization of a golden reference component. But as test demands increase, DFT will become increasingly important.