False failures still vex AOI
Stephen F. Scheiber, Contributing Editor -- Test & Measurement World, 10/1/2002
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Fig 1 Checking specific pin characteristics rather than simply matching connectors saves processing time in an AOI system. Courtesy of National Instruments. |
Using inspection as part of a test strategy presents its own challenges. In its simplest form, an inspection system makes pass/fail decisions by comparing images of a known-good, or golden, PCB with images of PCBs going through testing. But appearances can deceive even the best inspection system. A PCB that appears sufficiently different from an established standard may fail an inspection but still work properly. And, although inspection may avoid the need to exercise a circuit, it cannot guarantee the circuit works.
False failures often result because Automated Optical Inspection (AOI) systems look primarily for geometric shapes and other general characteristics of devices, solder joints, or PCB traces. Suppose you could teach the system what each solder joint, trace, and device type should look like, and the acceptable variations for each. Armed with that information, an "intelligent" AOI system could better determine if a PCB under test conforms to the conditions for a good product. Today, a computer can recognize a human face even after a person gets a haircut, changes hair color, or grows a beard. But in the PCB world, analogous changes still defeat conventional image-matching techniques.
Fail only bad PCBsAs always, the goal remains: pass good PCBs and fail bad ones, but without passing bad PCBs or failing good ones. Unfortunately, time spent analyzing images to accurately assess pass or fail conditions can reduce production throughput. In addition, placing an inspection system in a manufacturing line that doesn't already include one requires investments in time, people, and floor space, all of which most companies have in short supply.
Most PCB-manufacturing facilities still employ human inspectors, despite smaller board features that make manual inspection difficult. Human inspectors succumb to fatigue and distractions, and produce inconsistent results that reduce their effectiveness. Still, humans require little investment in capital equipment, and they're rarely fooled by conditions such as indistinct device labels and less-than-ideal lighting. Such marginal conditions often result in false failures from AOI systems.
Reports of false failures from AOI systems vary widely. Companies that inspect individual components report false-failure rates of a few percent or less. At PCB manufacturers, though, a false-failure rate of 80% of all failures is relatively common, and some AOI users consider that number low. One AOI vendor cites a goal of one false failure for every real failure—a 50% false-failure rate. Such high rates reduce production-line capacity and burden diagnosis-and-repair facilities. Decreasing such failures has become the goal of the AOI industry.
False failures result from a number of factors related to both inspection-system hardware and software. Until recently, camera resolution, computer processing speeds, and commercial software could not easily handle complex image-acquisition and image-analysis tasks in real time. In effect, adding an AOI system to a production line for PCBs often degrades throughput. Technology improvements now permit high-resolution cameras, faster computers, and more capable software that lets AOI system vendors and customers concentrate on issues related to testing PCBs rather than tweaking an AOI system. Still, AOI systems have limits, and they continue to identify false failures.
Limit inspection tasksOne way you can speed processing and help overcome false-failure problems is to limit inspection tasks to specific PCB areas, devices, and characteristics. Rather than checking an entire PCB, you could have an AOI system inspect only specific ICs, components, PCB traces, pads, and so on (Fig. 1). Checking a component's size and its solder joints, for example, would require examining only the edges of the device, not the entire package. Unfortunately, this type of inspection cannot check displaced components, because edges may fall outside of inspected areas. More critically, such inspections often cannot tolerate size and color changes in "identical" components from different vendors.
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| Fig 2 Intelligent AOI systems can "learn" about good and bad solder joints and, as a result, decrease false failures over time. Courtesy of Cognex. |
The inability of many vision systems to tolerate even minor differences between acquired images of production PCBs and "golden" PCBs leads to most false failures during inspection. To combat this problem, software suppliers now provide image-matching software that takes feedback from operators and uses it to modify how the AOI system matches image characteristics. An operator shows the system good and bad components and solder joints on a PCB and specifies the associated limits for each. During PCB production, the operator examines every failure to determine whether the system detected a real or a false failure. Feeding the false-failure information back to the inspection system helps it learn the range of acceptable variation in good PCBs. Over time, this approach can reduce the number of false failures.
In the learning approach, the characteristics of the first 100 or so PCBs determine the accuracy of the pass/fail decisions made for the PCBs that follow. Unfortunately, the requirement for a large number of "training" boards restricts this type of AOI to high-volume, low-mix manufacturing lines.
The learning approach also raises a question: Where does the first batch of golden PCBs come from? To start teaching an AOI system about good boards, manufacturers need a set of good boards that the AOI system will pass as good. This sounds a lot like the argument about which came first, the chicken or the egg. And it points out a problem with training an AOI system—you have to have boards that pass AOI tests to teach an AOI system about good boards.
If you have a high-volume production line, you can use an iterative process to find golden boards. But in facilities with smaller production runs and a large number of different PCB types, this requirement becomes unmanageable. John Arena, a marketing manager at Teradyne (N. Reading, MA), speculates that because most manufacturers produce short runs of PCBs, only about 10% of worldwide production lines have conscientiously implemented AOI. He concedes that far more companies have the necessary AOI equipment, but this "Catch-22" paradox of coming up with the first batch of golden training PCBs often prevents its wider use.
What about a model?As an alternative to matching solder-joint images, Philip Colet, VP of International Sales & Marketing at Coreco Imaging (Billerica, MA), suggests the electronics manufacturing industry create a mathematical model of what a good solder joint should look like. The model would include characteristics such as solder viscosity, reflow-oven temperature, solder-pad surface area, and so on, and would produce ranges of variations, also called guardbands, for acceptable solder joints. The resulting model would become the standard for evaluation of all joints on all PCBs.
In practice, an AOI system would produce 3-D profiles of solder joints based on images acquired at a variety of angles. Then, by comparing these profiles with data from the model, the system could make accurate pass/fail decisions. "Testing" such a model would require simulating variations in current flow, heat dissipation, hardness, resistance to vibration, and so on, and comparing the results to those obtained for solder joints under real conditions. Colet contends that using a model reduces the dependence of AOI systems on reflectance, joint size, and other factors that can vary without affecting the solder joint's actual performance.
Ensuring PCB quality remains a fast-moving target. To hit it, manufacturers increasingly turn to inspection to identify problems that defy conventional test. To help ensure success, smarter machine-vision systems must fill the gap to reduce false failures to more manageable levels without sacrificing throughput and fault coverage.
| Author Information |
| Stephen F. Scheiber is a consultant who writes frequently on board-test strategies. He holds bachelor's and master's of engineering degrees from Rensselaer Polytechnic Institute. He can be reached at sscheiber@aol.com. |




















