Wireless chipsets challenge testers

As wireless local-area networks (WLANs) become more prevalent, you are likely to start testing the challenging semiconductor devices that make WLANs possible. WLAN chipsets are complex, system-on-chip (SOC) devices that operate at high frequencies, but the price of these devices must be kept in line with consumer expectations; therefore, testing costs must be minimal. Because of the complexity of WLAN chipsets—they include mixed-signal, logic, embedded memory, and RF functions—test is an important factor in the overall cost of manufacturing, both in actual cost and its impact on time to market.

A typical chipset partitioning for a WLAN module is shown in Figure1. As with other wireless products, WLAN chipset integration levels continue to increase. Because of the integration of the baseband processor and medium access controller onto a single chip, the average chipset has already shrunk from five chips to four. Some WLAN chip manufacturers also use direct-conversion technology to combine the RF/IF and IF I/Q modulator/demodulator chips into one, reducing the number of chips further. (For a brief discussion of the WLAN market and the different, competing standards, see "WLAN: What it is and where it is used," below.)

Chipset functions

You'll have to allocate tests of the various chipset functions among the individual chips within the set. For the RF/IF chip, you must test the following functional elements: low-noise amplifier (LNA), downconverter, upconverter, local oscillator (LO), and driver amplifier. The main purpose of this device is to amplify the received RF signal using the LNA and then downconvert it to an IF signal for additional processing by the demodulator and baseband processor. The upconverter will upconvert the modulated IF signal from the modulator to an RF signal for amplification by the driver amplifier and, finally, the power amplifier prior to transmission via the antenna.

Functions within the IF I/Q modulator/demodulator chip that you must test include a variable-gain amplifier (VGA) and I/Q demodulator, plus another VGA and I/Q modulator. These functions operate as follows: After the received RF signal has been downconverted to IF, the VGA provides any necessary amplification to the IF signal. Next, the demodulator recovers the I and Q signals from the IF signal for further processing by the baseband processor, which recovers the data from the I and Q signals and sends the data on to the host appliance. The reverse happens with the modulator and VGA chain.

Baseband processors (BBPs) usually integrate media-access control (MAC) logic, baseband processing functions, host interfaces (such as USB, PCI, and CardBus interfaces), embedded memory, and analog-to-digital (ADC) and digital-to-analog converters (DAC). In 802.11a, for example, an orthogonal frequency-division multiplexing (OFDM) BBP typically supports all mandatory and optional data rates using binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), 16 quadrature amplitude modulation (QAM), and 64 QAM schemes. Additional features may include forward error-correction coding, signal detection, automatic gain control, frequency-offset estimation, symbol timing, channel estimation, and Wired Equivalent Privacy (WEP), an optional 802.11 mechanism intended to make WLANs as secure as wired LANs. BBPs also can perform receive and transmit filtering, frame encryption/decryption, and error-recovery operations as defined by the IEEE 802.11a standard.

Figure 1 Currently, WLAN chipsets typically divide into four devices: a power amplifier, an RF/IF stage, an IF I/Q demodulator, and a baseband processor integrated with a media-access controller.

You can test the logic and memory functionality of the BBP with standard digital test equipment. These tests typically include scan and BIST as well as standard functional digital vectors. At the I/Q analog interface, however, you must perform mixed-signal dynamic (AC) and static (DC) measurements. Measurements made on the I/Q receive (RX) ADCs and transmit (TX) DACs often include phase and magnitude balance, gain, offset, signal-plus-noise-plus-distortion to noise-plus-distortion (SINAD), integral and differential nonlinearity (INL/DNL), and filter characteristics.

WLAN chipset tests run the gamut from DC through analog/mixed-signal and up to RF, and they require a tester that performs both time-domain and frequency-domain measurements. For the RF portion, it's important to have real-time RF data processing with a wide-bandwidth receiver in the automatic test equipment (ATE) to speed up modulation and power measurements. Table 1 lists some example WLAN chipset-specified parameters.

Table 2 describes some specific tests for IEEE 802.11a chipsets. This table shows specs for the entire modem; specs will be more stringent for individual chips. Transmission-quality measurements for high data-rate digital communication systems traditionally include bit error rate (BER); for WLANs, similar measurements include Packet Error Rate (PER) for 802.11a and Frame Error Ratio (FER) for 802.11b. Measuring BER in a manufacturing environment can require lengthy test times on dedicated equipment that provides only limited diagnostics.

Error-vector-magnitude (EVM) testing offers an effective alternative for testing the performance of the WLAN demodulator and can be easier to implement than BER-like measurements. EVM, using full vector measurements (magnitude and phase), is called out in several system standards, including GSM (the European Global System for Mobile Communications), PHS (the Japanese Personal Handy Phone System), and WLAN.

EVM quantifies the errors in digital demodulation, is sensitive to any signal impairment that affects the magnitude and phase of a demodulated signal, and can be performed on various ATE systems. To demodulate the data, a test system has to determine the exact amplitude and phase of the received signal for each clock transition. These values define the actual or measured phasor signal. EVM is the distance between the end points of the measured and reference phasors (that is, the magnitude of the difference vector); you can express it as a percentage of the peak signal level (typically, the constellation's corner states).

The utility of scattering parameters (S-parameters) has made them the dominant method for measuring RF and microwave devices and networks. By measuring just the complex voltage waves transmitted through and reflected from the ports of a network, usually embedded between a 50-Ù load and source, a test system can calculate S-parameters that completely characterize the network in simple gain and reflection coefficient terms (which can be easily related to power gain and mismatch loss). When used to characterize RF and microwave components that operate together (such as amplifiers, transmission lines, and antennas), S-parameters allow the interactions between components to be simply predicted and calculated, making it possible to maximize performance in areas such as power transfer, directivity, and frequency response.

Besides being conceptually simple and analytically convenient, S-parameters are easier to measure and work at higher frequencies than other kinds of parameters because the DUT is terminated in the characteristic impedance of the measuring system. The characteristic-impedance termination is accurate at high frequencies, does not require tuning to terminate a device, enhances stability, and allows broadband swept measurements. Vector-calibration standards for S-parameter measurements are widely available and allow full 12-term error corrections. As a result, measuring the gain of a device using S-parameters ultimately provides more accurate results than using basic power measurements.

WLAN transmitter tests, at least for the IEEE standards, include maximum allowed power (per FCC regulations), transmit spectrum masks (that is, specified power levels at various offsets from the center frequency), allowed relative constellation errors (as a function of data rate; EVM can be used here), spectral flatness, spurious signals, frequency tolerance, and frequency leakage. For low-cost test, the test system must be able to do all these tests rapidly. In particular, the test system's RF receiver should have a wide enough bandwidth to gather all the required data in one acquisition. For example, with the 802.11a transmit spectrum mask, the receiver's bandwidth should be greater than 25 MHz, or test will require multiple acquisitions to collect the power out vs. frequency information.

In the WLAN market, where transmitter power is limited and receiver sensitivity is often a key differentiating specification, characterizing and specifying the match at the transmit and receive ports of the chip is important. Any mismatch at these ports will result in a transmitter sending less power, or in a receiver detecting less power, potentially placing the part at a competitive disadvantage.

General techniques that are widely used for improving the throughput of testing complex devices can also be applied to WLAN device testing to lower test times. One option is to use multisite testing for testing multiple WLAN devices in parallel. Of course, multisite testing adds overhead associated with the tester architecture, the handler interface, and the DUT. For example, larger data transfers are required when testing multiple devices at one time. Also, multisite testing requires high levels of measurement repeatability from site to site to ensure accurate measurement results. Yet, the overall reduction in test time can still be sufficient to justify using this approach.

Another way to improve tester efficiency is to test intellectual-property (IP) blocks simultaneously. With this option, you can test different IP cores at the same time within a hierarchical SOC design—obviously a major benefit when testing complex ICs such as highly integrated baseband processors or single-chip WLAN modules with both RF and baseband sections. Being able to test multiple cores at the same time significantly shortens test times while ensuring tester resources are being used at full capacity.

To support simultaneous testing, the tester pins are based on a modular architecture that can be configured to provide all the testing resources needed to target an IP core. For the baseband portion of a chip, the tester configures the pins on the fly into a port— a collection of pins (one or more) defined for an independently accessible IP core. Each of these ports can execute an independent sequencer program, enabling parallel IP core test execution. For example, one port can be testing a memory core while another port on the same tester might be exercising a block of mixed-signal circuitry in a WLAN single-chip baseband processor and media access controller. Each port can operate at a different clock speed while using completely different testing resources.

You can take several steps to improve the testability of a WLAN chipset. To ensure the highest quality production test, compare the results measured for the first few devices you test on your production tester with R&D results; don't begin high-volume manufacturing until they correlate well. Sharing the same modulation signals, calibration techniques, and measurement algorithms will improve this correlation. When design tools, characterization or benchtop equipment, and production test equipment can share a pool of hardware and software resources—including signal definitions, analysis techniques, calibration methods, and modulation/demodulation libraries—a synergy occurs that accelerates time to market, enhances "correlation to bench," and enables more robust designs with fewer design turns.

Also, a simple DUT board design speeds test program development time. The more testing capabilities the ATE system offers, the simpler the DUT board design can be. Streamlined DUT fixtures ensure better repeatability across multiple testing sites and ease handler interface requirements, helping to promote higher yields and lowering the cost of test.

The last piece of advice is to consider testing from the outset of the design cycle to help lower the cost of testing and improve time to market. It helps tremendously if the designer has the target test system in mind when designing the chips. To that end, design and test should work as a team over the entire design cycle. This is especially critical for WLAN testing because of the demanding RF testing requirements.

Evolving standards, increasing chip complexity, and price erosion are challenging the semiconductor industry. Yet, WLAN appears to be overcoming these hurdles and heading for a bright future. As WLAN devices become more established, test engineers will need to become familiar with their complexity. With the right mix of testing resources and careful thought on how to increase tester efficiency, test engineers will be able to test WLAN devices while keeping the cost of test at acceptable levels.