Place your bets: BIST or scan

As integrated circuits accommodate ever more transistors, the number of test vectors needed to test logic ICs rises dramatically. Design-automation companies are pursuing two design-for-test (DFT) strategies—test-pattern compression and built-in self-test (BIST)—to minimize the number of test vectors needed for adequate fault coverage. Meanwhile, ATE companies are providing test systems that can handle either approach.

The first DFT strategy extends the traditional automatic test-pattern generation (ATPG) used in scan-based chip designs (see "Scan and BIST basics," p. 38). As with standard ATPG, the new strategy requires external storage of test vectors on an ATE system, but it employs deterministic compressed external test-vector schemes to minimize ATE vector-buffer-memory requirements. On-chip DFT circuitry expands the compressed vectors into the full vector sets necessary to exercise internal scan cells; additional DFT circuitry compresses test results for transmission back to the ATE for pass/fail determination and fault diagnostics.

The second strategy employs on-chip BIST circuitry to generate pseudorandom test patterns. Generating a sufficient number of these patterns will provide a high probability that the total pattern set will exercise each potential defect within the BIST-enabled circuitry, yielding a telltale output signature that indicates whether the circuitry is good or bad. All that's necessary from external ATE is a signal to initiate the test and the ability to respond to BIST pass/fail results.

Proponents of the ATPG and compression strategy contend that only a deterministic set of test vectors can provide adequate fault coverage. BIST proponents counter that they have developed enhancements that let BIST achieve the fault coverage of ATPG.

The emergence of ATPG compression schemes represents the latest stage in the evolution of ATPG tools. Says Cy Hay, marketing manager at Synopsys Test Automation Products, "Every commercial ATPG tool supports dynamic and static pattern merging, and this type of compression is universally required and used when generating test patterns for manufacturing." Such approaches alone hold promise for testing new designs containing a relatively modest sub-10-million gates. Andrew Levy, director of marketing at Teseda, says, "We believe that 'standard ATPG' will continue to be the norm, [but] it is likely that the fault models used by ATPG will change. The stuck-at model, which has served so well for many years, will likely be supplemented with others, such as coupling faults."

Even at the 10-million-gate level, standard ATPG without compression can suffice. "Some designs Cadence processed containing more than 10 million gates had reasonable test times because they did not require a large number of test vectors," says Lee Todd, product marketing director at Cadence Design Systems. He adds, however, that "Compression technology will take the guesswork out of it, providing more certainty that the tests will fit on the ATE regardless of the specific design."

Indeed, for 10-million-and-up-gate designs, some compression will become the norm. Synopsys' Hay explains that "DFT techniques such as test points and deterministic logic BIST can significantly reduce test-pattern volume and test application time beyond what ATPG compression alone can provide, but reduction from these DFT techniques is on top of ATPG compression."

When asked whether low-cost ATE systems with large, flexible buffer memories will obviate the need for test-pattern compression, Hay says, "Not really. New ATE systems optimized for structural testing may help maintain or improve test quality as test data volume explodes. But other issues, such as test application time and multisite/limited-pin testing, are also critical."

Deterministic patterns Pattern # Red die Yellow die 1 1 1 2 1 2 3 1 3 4 1 4 5 1 5 6 1 6 7 2 1 8 2 2 9 2 3 10 2 4 11 2 5 12 2 6 13 3 1 14 3 2 15 3 3 16 3 4 17 3 5 18 3 6 19 4 1 20 4 2 Figure 1 BIST employs sufficient random patterns to ensure a specified probability that at least one pattern will examine each potential defect. Here's a quiz: If each pattern corresponds to a throw of these dice, and all possible combinations of rolled values are required to detect all defects, how many throws are required for 98% fault coverage? How many deterministic patterns are there? (Note that for the purposes of this question, a one on the yellow die and a two on the red die represent a different patterm from a one on the red die and a two on the yellow die.) Send your answer to rnelson@tmworld.com.

Greg Aldrich, ATPG product marketing manager at Mentor Graphics, agrees that new ATE formats won't reduce the need for compression: "These systems may offer huge memory behind each pin, but what's important is throughput," and the time required to clock all the stored bits of uncompressed ATPG into a DUT would kill throughput.

Hay does note that going forward, "What's fundamentally changing is that the choice of an ATE platform will be driven by DFT methodology, not the other way around. For example, someone using traditional full-scan DFT may chose a different tester than someone using our SoCBIST. In the past DFT was implemented to match the limitations of a standard ATE platform, but now this approach leads to unacceptable tradeoffs between test quality and testing cost."

To that end, ATE makers ranging from the traditional "big iron" companies to start-ups like Teseda are offering test platforms that emphasize DFT. Nevertheless, designers will still face pressure to adapt their DFT strategies to the existing, yet less-than-ideal, ATE systems that their companies already own. Says Cadence's Todd, "The lowest-cost ATE is the one already paid for and fully depreciated, sitting on the test floor. Because of the fairly large base of existing test equipment, the most effective solutions for controlling test costs will involve a combination of tools that allow the chip designer or DFT engineer to leverage the best capabilities available on the target tester."

BIST aficionados suggest that deterministic ATPG, even with compression, simply won't be adequate for emerging SOC designs. Stephen Pateras, director of engineering at LogicVision, has written that all ATPG falls short, and he has enumerated what he calls the "three myths" of ATPG (Ref. 1): ATPG achieves better fault coverage, it supports at-speed test, and it scales with growing chip sizes. None of those is true, Pateras wrote, adding that BIST can provide superior defect coverage because its pseudorandom patterns can detect each defect many times. He cited unnamed studies that show that true defect coverage, not just stuck-at fault coverage, is proportional to the number of vectors that exercise a particular defect.

Synopsys' Hay counters this last argument: "There are well-established fault models [in addition to stuck-at models] for deep-submicron defects, such as transition faults, path-delay faults, and bridging faults. Unlike random patterns, ATPG and deterministic logic BIST can predictably achieve high test coverage of these as well. It is not a question of whether an unlimited number of random patterns can detect more defects; it is a question of how to detect more defects in a reliable, measurable, and economical way."

ATPG proponents also contend that to keep the required number of pseudorandom patterns under control, BIST approaches require excessive numbers of test points. Says Mentor's Aldrich, "I don't know of any BIST that will do ATPG levels of fault coverage without lots and lots of test points," and getting from 96% to 98% coverage can cause test-point requirements to explode. "Millions of cycles of random patterns can detect a single fault in many different ways," he says, but ATPG can do it much more quickly with deterministic vectors. Mentor, Aldrich says, positions its logic BIST product for system-level test—which can be performed on BIST-enabled chips without requiring an expensive ATE system.

Cadence Fellow Bernd Koenemann worked with DFT at IBM before Cadence acquired his division last year. He shares Aldrich's viewpoint. "We pioneered the original BIST concepts at IBM in the early 1980s and have supported BIST since then," Todd says. "BIST has many advantages, [but] our experience is that even after inserting many test points to improve fault coverage, DFT engineers still need to 'top off' ATPG tests to bring the logic BIST fault coverage up to the traditional ATPG level."

Figure 2 Moving forward, it's likely that combinations of ATPG and BIST will cooperate to ensure testable chips, and the two approaches might begin to develop more similarities than differences. Says Louis Unger, a test consultant at A.T.E. Solutions, "BIST vectors do not always have to be pseudorandom." He has developed a board-level built-in test capability that combines deterministic and pseudorandom patterns, and he suggests such an approach might work for chips as well.

Mentor's Aldrich concludes that the application will dictate the test strategy: "What do you want to do? Manufacturing test on a production ATE system or in-system test with minimal external tester resources? And keep in mind that ATPG, logic BIST, or some combination of both aren't the complete test story. Your chip is likely to be half memory, which has its own test requirements."

*The original version of this article attributes a quote about IBM to Lee Todd. The quote should have been attributed to Bernd Koenemann, Cadence Fellow. Lee Todd did not work at IBM. Updated June 9, 2003.