Testing EEPROM-calibrated mixed-signal ICs

Traditionally, semiconductor manufacturers used Zener- and link-trimming to calibrate parameters such as output voltage on analog ICs. They performed the trimming at the wafer level, using additional pads designed specifically for the purpose. The trimming process effectively locked an IC's target parameter, making reversal (or recalibration) almost impossible.

Mixed-signal MOS devices such as this one used EEPROM cells to store calibration data.

Initial efforts in applying this approach included indirect test of the EEPROM cells themselves. This indirect approach involved read/write cycling EEPROM bits, programming each bit, baking the wafers, and, at final test, looking for any parametric drift that would suggest that EEPROM calibration data didn't survive the wafer-bake stage. With this approach, however, least-significant-bit EEPROM-cell failures could result in test escapes or poor process yields.

A direct EEPROM test approach overcomes this drawback, providing for direct data-retention test at the package level. In this approach, a final-test system looks for wafer-level data, whose presence would indicate a good device. If the tester doesn't find that data, it performs a trim-parameter test to determine whether it is re-testing a previously programmed good device. Finally, the tester attempts to reprogram rejected devices with the original wafer-level data to facilitate later retest. A single test program can accommodate fresh and rejected as well as good but previously programmed devices.

To learn more, read a paper by C.H. Lim of National Semiconductor at www.tmworld.com/EEPROMcal.