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DSM drives signal-integrity concerns

Rick Nelson, Executive Editor -- Test & Measurement World, 9/1/2003

At deep-sub-micron (DSM) geometries, you'll find that increased coupling capacitances, current densities, and interconnect resistances can combine with lower power-supply voltages to present signal-integrity (SI) challenges that can't be met using traditional IC design techniques.

Capacitive coupling can allow an aggressor net to induce a noise glitch on a passive victim net. The coupled energy may be sufficient to cause an unintended transition, which can propagate to a bi-stable device that captures it, leading to a functional failure.

As geometries shrink, interconnects become narrower and taller, increasing wire-to-wire capacitances and producing crosstalk-induced noise and delay. In addition to capacitance-induced problems, low power-supply voltages and increased power-supply rail resistances can lead to IR drops sufficient to reduce noise immunity and to increase cell delays, leading to setup violations. Also, the high current densities of DSM designs generate electromotive forces as electrons collide with a device's metal lattice structure. These forces can result in electromigration, leading to voids and shorts, particularly in power and ground grids. The self-heating characteristics of wire can worsen electromigration and cause thermal-mechanical stress that can lead to interconnect failures.

Rajiv Maheshwary, director of marketing for static timing products at Synopsys (Mt. View, CA), contends that SI issues must be addressed with a design strategy that analyzes an IC's SI characteristics and automatically makes repairs. To that end, the company's Galaxy design platform generates noise maps and reroutes potentially troublesome nets before physical synthesis.

For more information on SI and how to ensure it, see www.synopsys.com/products/signal_integrity/signal_integrity.html.

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