Learning quickly from I_DDQ

Determining whether I_DDQ failures result from design errors, test-vector pattern problems, or silicon defects can be time consuming and costly. You can simplify the investigation into why abnormal I_DDQ behavior occurs by measuring I_DDQ as a function of temperature and generating the best-fit equation. We employed this method on a 0.18-µm process, but you can use it for any process to determine the status of your vector patterns, your design, and your silicon, all within hours.

Common I_DDQ tests compare I_DDQ current patterns and then look for statistical outliers, which represent suspected defects. During characterization, you can use an I_DDQ temperature profile to ensure the validity of test vectors and rule out design errors. During manufacturing, you can determine whether outliers represent real defects by comparing the temperature profile of the minimum and maximum I_DDQ currents of good and bad parts.

The formula for the sub-threshold current of a MOS transistor is (Ref.1):

I_DDQ = (W X_C/ L)exp(-k V_t/ T) (1)

where W is the transistor width, L is the transistor length, X_C and k are constants, V_t is the threshold voltage, and T is the temperature.

More simply,

I_DDQ = C₁exp(C₂ T) (2)

where C₁ and C₂ are constants.

Generally, a defect affects the maximum I_DDQ value, so the minimum I_DDQ temperature profiles for both good and bad parts would conform to equation 2, but the maximum I_DDQ temperature profile of a bad part would not.

A good I_DDQ measurement must meet three requirements:

• The correlation coefficient, R², of the I_DDQ current vs. temperature data must be 0.98 or higher. Our data has shown that an R² of 0.98 or higher represents good correlation with equation 2. This value does not depend on the fab processes or devices.
• C₂ must range from 0.02 to 0.05, based on our experience with various products fabricated using a 0.18-µm process; C₂ is generally smaller for faster processes.
• The intercept value, C₁, represents the average I_DDQ value. You can calculate this value or estimate it based on the history of other parts fabricated using a given process. This value increases for faster processes (which exhibit smaller transistor length, L).

Three examples show scenarios where I_DDQ temperature profiling is beneficial: design errors, test-vector problems, and silicon defects.

During characterization, good I_DDQ measurements will show that I_DDQ and temperature correlate in accordance with equation 2. Plots A and B in Figure 1a represent two good I_DDQ measurements (which differ because of fab process variation). Curve-fits for plots A and B of the five measurement points yield these results:

For plot A:

I_DDQ = 0.6752exp(0.0343 T), and R² = 0.9982

For plot B:

I_DDQ = 0.4574exp(0.0347 T), and R² = 0.998

Next consider the part represented by plot C in Figure 1a:

I_DDQ = 14.648exp(0.0014 T), and R² = 0.538

Figure 1. You can fit curves to IDDQ-vs.-temperature data points to help identify (a) design and test-vector problems and (b) silicon problems.

It's not clear how to isolate the problem. Equation 2 shows that I_DDQ should exponentially increase with temperature. But plot C shows that the I_DDQ values at both 0°C and 20°C are about the same. Furthermore, the current at 0°C should be much less than 9 mA. These factors suggest that a current component whose response is inversely proportional to temperature must also be present.

When we analyzed the device, we located a resistive short (caused by a defective mask) of about 300 Ω between P diffusions; plot D represents the resistive short's current response with temperature. Plot E shows I_DDQ current with the resistive short removed. Plot E's equation meets the three criteria of the good I_DDQ measurements:

I_DDQ = 0.328exp(0.035 T), and R² = 0.9963

Another scenario involves poor I_DDQ vector patterns. Figure 1a plots F and G show the current measured with bad I_DDQ vector patterns:

For plot F:

I_DDQ = 8.16exp(0.0095 T), and R² = 0.9165

For plot G:

I_DDQ = 0.457exp(0.0347 T), and R² = 0.998

For plot F, C₂ and R² do not meet the good I_DDQ measurement criteria, but for plot G they do. Why the difference? Plot F represents data taken with V_DD of 1.5 V; for plot G, V_DD was 1.0 V. After some analysis, we found that the I_DDQ vector patterns did not put all the circuits in quiescent states at the nominal 1.5 V_DD, resulting in floating current. With V_DD reduced, the floating current disappears.

This floating current (drain-source current, I_DS) exhibits the temperature response shown in plot H in Figure 1a. In CMOS, I_DS decreases as temperature increases for strong inversion conditions. Plot I represents the I_DDQ measurements with V_DD at 1.5 V after we fixed the vector patterns:

I_DDQ = 0.7776exp(0.0347T), and R² = 0.998

When high I_DDQ failure rates occur in production, temperature profiling can ensure that good parts are not rejected and bad parts are not shipped. Figure 1b represents a temperature profile of one failing part (plots J and K) and one passing part (plots L and M). This lot has about 30% I_DDQ failure rate, which is much higher than average.

Typically, a part fails I_DDQ tests either with respect to the absolute maximum limit (for all vector patterns, I_DDQ exceeds the maximum limit) or with respect to current ratio (only some vector patterns result in excessive currents). We chose to apply the current ratio method described in Ref. 2 for our production test, which employed 200 I_DDQ vector patterns.

Since the assumed-defective parts in Figure 1b fail the current ratio while the passed parts are defect free, then the following should be observed:

• Minimum and maximum I_DDQ values of the 200 patterns applied to passed parts should exhibit very similar temperature profiles.
• The minimum I_DDQ of a failed part should exhibit a temperature profile similar to that of the minimum I_DDQ of a passed part, and it should also meet the three criteria for good I_DDQ measurements.
• The maximum and minimum I_DDQ values of the failed part should exhibit different temperature profiles, and the maximum I_DDQ value will not meet the three criteria of a good I_DDQ measurement.

Table 1 summarizes the plots in Figure 1b. The value C₂ for plots J and K differ: For plot K, C₂ is 0.0317—within the expected range. For plot J, C₂ is 0.0151—which is too low. R² of plot J is 0.9179, while R² of the plot K is 0.989.

These two conditions confirm that plot J (max I_DDQ vector) represents defects and that plot K (min I_DDQ vector) does not for the same part. This confirmation shows that the I_DDQ failure is real and the part should be rejected. As for plots L and M (passed I_DDQ), all C₁, C₂ and R² values meet the criteria for the good I_DDQ measurements. This confirmation at least shows that no defect has been detected with the I_DDQ vector patterns.

In most cases, an R² value lower than 0.98 is enough to show that the I_DDQ measurements are not good (the R² value does not depend on the fab process). Unlike R², the C₁ and C₂ components do depend on processes and devices, so comparison of known-good measurements to a questionable one is appropriate.