Open architecture supports parallel test

As the transistor geometry shrinks, more transistors are packed on to a single chip, reducing manufacturing cost on a per-transistor basis. The result, however, is more transistors to test; hence, test cost increases on a per-chip basis for SOC and other logic devices.

Falling commodity DRAM test costs per site suggest a method for controlling logic test costs per chip. Numbers are based on an Advantest T55XX Series tester.

Yet, despite the increasing densities, per-chip test costs for commodity memories have actually fallen. DRAM per-site cost (tester + handler) was approximately $400k at the end of 1997; today, per-site cost is approximately $27k (figure). Because of such reduction, memory test cost is a non-issue—test cost discussions focus on SOCs and microprocessors.

Test-system vendors employ massive parallelism to control memory test costs. In 1997, 32 DUTs were tested in parallel; today, 128 DUTs are tested in parallel, increasing throughput from 3000 devices/hr to over 12,000 devices/hr, achieving test productivity of about 1 Gbit/s.

For SOCs and microprocessors (logic test), design-for-testability (DFT) and built-in self-test (BIST) have distracted IC manufacturers. DFT and BIST shift costs from the test floor to the design engineer, but it is arguable if they reduce the overall cost. Lessons from memory test dictate that parallel test is a good way to control the test cost on a per-chip basis. The recent Open Architecture Initiative, including the efforts of the Semiconductor Test Consortium (www.semitest.org), incorporates this key lesson in a basic feature set of the open-architecture test system. To learn how the emerging open architecture addresses parallel test for SOCs and other logic devices, you can read my paper "Why Open Architecture Tester Should Support Parallel Test" at www.tmworld.com/parallel.