DFT to help ATE tackle high-speed test

Boeblingen, Germany—Design-for-test (DFT) technology is a key complement to ATE systems. That's the conclusion arising from interviews conducted at Agilent Technologies' facility here, where the company develops and builds its 93000 Series system-on-chip (SOC) testers. DFT will be particularly important for the niche at which the company is aiming its 93000 line.

A design-for-test input could inhibit the generation of skip sequences during test.

Application consultant Hubert Werkmann elaborates on the challenges in working with prototype PCI Express chips. He cites as an example two interconnected PCI Express devices. Each must operate within a transmit/receive clock-frequency tolerance, but the two are not frequency-locked.

In normal operation, a receiver channel's FIFO buffers collect data decoded from a serial-link input and disburse it synchronously with the receiver system clock. For situations in which the transmitter clock is slightly faster than the receiver clock, receiver buffer overflow would eventually occur. To compensate, a transmitter inserts "skip sequences," which the receiver recognizes and discards.

The skip-sequence insertion operation creates a problem for jitter tests (and other tests that rely on real-time compares), which might involve a device under test (DUT) and a known-good device operating in a loop-back mode (see figure). An ATE system such as the Agilent 93000 SOC Series NP model can readily perform such tests, but jitter measurements made on a DUT's self-generated skip-sequence bits would not provide meaningful information about jitter that the DUT might add to external signals. An ATE system could be programmed to recognize these sequences and ignore them. But that, says Werkmann, would not be practical.

A better alternative, he says, is to design into PCI Express devices a test-mode input that inhibits skip-sequence generation. For this and other test situations, he suggests device makers and ATE makers should agree on an economically reasonable combination of DFT capability and ATE performance. You can expect both camps to make headway over the next year as PCI Express and other Serdes-based serial links make their way into next-generation computer systems.

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Rick Nelson, Executive Editor rnelson@tmworld.com