Put "free" silicon to work

During the past two decades, steadily increasing integration levels coupled with steadily decreasing costs for SOC and ASIC development have mesmerized the high-tech industry. But now, a 20-year dream-come-true is becoming a nightmare. Integration levels continue to double every 18 months or so, but the associated development costs are no longer falling—in fact, they are rising substantially. For many companies that once developed dozens of ASICs and SOCs each year, the sticker shock of new technology has resulted in fewer design starts.

Spurred on by the basic economics of supply and demand, new techniques for implementing cost-effective designs are emerging. Innovations in lithography, mask fabrication, packaging, and test can all make your job easier. In addition, you can use platform or structured ASICs as well as ever larger and more complex field-programmable gate arrays (FPGAs) with embedded intellectual property (IP) to ease the economic burden of bringing new products to market.

Although you might find FPGA-based designs attractive, performance issues or product-differentiation feature sets might dictate your use of ASICs or SOCs (see "ASIC, SOC, or FPGA? "). And as a Test & Measurement World reader, you probably find lithography innovations beyond your control. Nevertheless, you can make use of your influence within your company's design and test groups to encourage compliance with the suggestions outlined here. These suggestions can help leverage the higher cost incurred for ASIC and SOC design styles. By incorporating them into your company's designs prior to fabrication, these suggestions can help lower the risk of an all-mask change or aid in diagnostics in order to improve yields.

These suggestions all make use of the "free" silicon contained within a design. "Free" silicon is any unused area that does not contain a gate or a metal interconnect. In past years, designers have filled these areas with their names, company logos, and even wedding announcements. In today's economy, this "free" silicon can be put to better use.

The main design goal is to maximize the silicon with as much functionality as possible and minimize the open silicon areas. This goal can be achieved in two ways—increased analysis capabilities and risk mitigation.

You can improve analysis capabilities by adding logic-test circuitry, process-test structures, and I/O pads to your chips. First, you can add extra test logic circuitry to dramatically reduce the required number of test vectors (and number of I/O pads required to get stimulus and response vectors into and out of the chip), which helps minimize the cost of your production test equipment. Indeed, for some designs, the majority of development costs are associated with testing. Each new generation of silicon pushes the limits of performance and extends the number of gates and I/O pads. Without preliminary analysis of design-for-testability issues (for wafer probing and packaged tests conducted during burn-in or post-burn-in phases, for example), test cost can get out of control and test throughput can suffer.

Built-in self-test (BIST) structures can help test memory and logic and can even perform high-speed testing. Other test logic, such as embedded compression, can reduce the number of vectors required to effectively test a device. Along with reducing test costs, the additional logic will help production and failure-analysis personnel diagnose yield losses or returned material from customers.

Second, you can add extra test structures to help identify process variations. Each new generation of silicon exhibits unique physical phenomena that must be measured. A silicon vendor will automatically insert many of these structures, but you can add others to help you understand how effective various fault models (such as stuck-at, open, delay, or resistive) are for new technology nodes. The information you glean may be useful when you experience catastrophic yield loss during wafer or package test.

It is easy for a product engineer to check the parametric data for abnormal processing. This data is normally taken prior to wafers being shipped to the wafer-probe stage for functional test. Problems identified with test structures relate to fabrication issues, ranging from improper implants, under- or over-etching, missing processing steps, incorrect masks, and so on. Often, trend analyses of this data can identify areas on the die or in the fabrication process that process engineers could modify to improve yield.

Third, for core-limited designs that have additional space in the I/O pad ring, you can add additional I/O pads to help improve the access to embedded functions. If free pad-ring space isn't available, you might be able to implement additional test modes that multiplex some I/Os between their normal functional mode and a specific test operation. Adding I/O pads allows for cost reductions as well as better failure analysis.

In addition to increasing analysis capabilities, risk mitigation can also reduce costs. It can be accomplished with three methods.

First, you can add to the free silicon areas extra gates (or spare gates) that represent logic already contained in the design. You can spread these spare gates around the design or concentrate them in an area known to have a high likelihood of change.

An example of this would be in the development of a new interface or state machine. While these extra gates need to have their inputs tied to power or ground to help minimize power dissipation, they provide the opportunity to correct an error, should one occur, without resorting to a completely new mask set. Often, these spare gates allow trivial errors to be corrected by modifying just a few masks rather than the entire set. With mask-set costs reaching $1 million and beyond, any technique that can help reduce the chances of an all-layer change is worth the investment. And this method is easy to implement during design implementation.

Second, you can help mitigate risk by adding an alternative implementation for high-risk components. You can add additional test logic that allows your alternative module to be substituted for the high-risk version. If you use programmable logic, you can swap between high-risk and safe implementations with a minor mask revision or a software change.

Third, if you have included sufficient safeguards for your current design and still have room available on the chip, you can use the free space for new IP blocks that you are designing for future products. This strategy helps generate a "free" design spin to prove the IP before it's needed in a specific product. (If you don't have room for next-generation IP in today's design, you will find it useful to create a single stand-alone test chip that contains all your IP blocks under development. This strategy helps leverage the development and verification costs over multiple IP blocks and reduces the risk for production designs. Always remember the golden rule for any reuse program—use only proven IP.)

Although the methods discussed here do not compensate for poor design, verification, or implementation, they do suggest ways that you can capitalize on "free" silicon. Given the additional costs in developing SOC or ASIC designs, it would be a shame to lose the differentiation advantage with long re-spin cycles.

For more information on semiconductor test, visit www.tmworld.com/ic.