HyperTesting

High-speed data buses are moving from high-end communications applications to high-volume consumer products, and they are bringing with them significant test challenges. To address these challenges, test vendors are maneuvering to develop cost-effective test strategies for ICs that implement standards like HyperTransport and PCI Express.

Complicating the test process are the unique characteristics of these high-speed parts (see "Why source-synchronous? "). Transmitter output data is synchronized to the source device, and a receiver, or test system, must adapt—effectively speeding up or slowing down to keep pace with the transmitter.

Figure 1. NP Series pin-electronics cards for 93000 Series ATE systems embody source-synchronous test capabilities that customers can access on a pay-per-use basis. Courtesy of Agilent Technologies.

Each approach provides unique challenges to test systems, which have traditionally expected to find valid data during tester clock transitions. In fact, says Neil Kelly, chief technology officer at LTX (Westwood, MA; www.ltx.com), high-speed devices "represent the biggest change to tester architectures since central-resource testers gave way to per-pin configurations."

Steve Lomaro, marketing director at NPTest (San Jose, CA; www.nptest.com), agrees that source-synchronous devices represent a significant change in test approaches. "The forces that historically have driven ATE design have been pin count and speed," he says. Those parameters are still driving tester development, he continues, but he adds that the test community is increasingly focusing on high-speed bus devices.

Figure 2. Teradyne's SSPE pin-electronics option offers same-cycle source-synchronous test capability, in which a DUT clock, instead of a tester clock, latches test data.

Which technology is more difficult to test—clock-forwarding or embedded clock? The general consensus is that both are difficult but pose different challenges, with the embedded-clock approach ending up slightly more difficult. Clock-forwarding testers must accommodate the extra clock signal, but that's not as much of a challenge as dealing with embedded-clock performance. Says Kelly, "With an embedded-clock device, a tester must extract the clock information from the data stream, usually using a phase-locked loop that must be built into the tester hardware." In addition, he adds, embedded-clock devices usually operate at higher data rates, as the rationale for their use is to eliminate the clock-to-data skew that would be problematic at such rates. After all, he says, "With embedded clocking, the clock is guaranteed to travel the same distance as the data."

Mike Kondrat, marketing director at Credence Systems (Milpitas, CA; www.credence.com), which in February announced its intention to acquire NPTest, points out that embedded-clock schemes also require a training mode, in which transmitters start spewing data and receivers learn to extract the clock and decode the data. A tester for such parts must be sufficiently flexible to emulate training modes among the multiple embedded-clock data lanes of a device under test.

Figure 3. Native-mode tests mimic the environment a DUT will see in the real world. Courtesy of Credence.

Guido Schulze, an application consultant at Agilent Technologies (Boeblingen, Germany; www.agilent.com), elaborates on loop-back tests. "Loop-back has become an accepted solution on old technologies like 10BaseT (Ethernet). With devices implementing new high-speed standards, though, it's important to do parametric tests to determine how good the (DUT's semiconductor fabrication) process is."

ATE vendors address source-synchronous test in different ways, either integrating the capabilities into their standard test systems or offering them as options. Dave McGraw, product manager at Teradyne (Boston, MA; www.teradyne.com), notes that Teradyne offers as options for its high-end Catalyst Tiger platform a Serdes port qualifier, a same-cycle pin-electronics function, and a 10-Gbps digitizer. In contrast, Agilent Technologies, says Schulze, builds source-synchronous capabilities into its line of NP pin-electronics cards, allowing customers to access them on a fee-per-use basis.

Apart from the way they package their source-synchronous test capabilities, companies pursue different technological approaches. Kondrat touts what he calls "native mode" testing for Credence's Octet platform; native mode tests, he says, mirror the real-world application the DUT will face. McGraw touts the ability of Teradyne's SSPE option to capture DUT data in real time using the DUT output clock—which McGraw calls "same cycle" source-synchronous performance. Kelly and Lomaro say LTX and NPTest systems, too, provide similar performance, although those firms haven't adopted the "same cycle" terminology.

Schulze says Agilent takes a different approach: "Our standard solution now is to use the tester timing as the reference. Our goal is to provide the highest bandwidths and levels of accuracy." With the "same-cycle" approach, he says, "You need some time to distribute the clock. For semiconductor die, the distances involved are a few millimeters, and the time is insignificant. A tester, though, adds centimeters. If you compensate for that, you need to add active components, cutting bandwidth. Our goal is to measure the customer's DUT, not our pin-electronics card."

Which approach ultimately prevails will depend on whether test engineers find that bandwidth and accuracy or same-cycle real-time performance is most effective at weeding out the defects that emerge most often as source-synchronous device production ramps up.

For late breaking news on high-speed serial I/O test, see www.tmworld.com/bist_assist.