Design for life

Reducing the cost of production test has been a key goal of design for test (DFT) and built-in self-test (BIST), but you can use the techniques to support a product throughout its life cycle to:

• speed up debug and failure analysis,
• improve time to yield,
• maximize manufacturing yield,
• assist in system-level production test, and
• enable field test and reconfiguration.

These capabilities are all emerging as DFT and BIST vendors refine their offerings and investigate the uses to which their customers put those products. Perhaps most dramatic in this respect is the experience of LogicVision (www.logicvision.com). Vinod Agarwal, company founder and chief strategist, has repeatedly stated that his goal was to cut the cost of test by making "big iron" ATE obsolete.

Figure 1. Embedded test can improve yield by minimizing guardbands, resulting in rejection of fewer good devices. Courtesy of LogicVision.

Healy doesn't see embedded test IP such as LogicVision's completely displacing traditional scan-based automatic test-pattern generation (ATPG) tools. He predicts BIST will be indispensable for multicore devices having 5 million gates or more but that ATPG alone will suffice for smaller designs.

Healy cites the debugging features of his firm's BIST offerings as critical to increasing time to yield, but debugging prowess isn't the sole domain of BIST solutions. Synopsys (www.synopsys.com), for example, has integrated its TetraMAX ATPG tool with Agilent Technologies' (www.agilent.com) 93000 test system to derive debug information from test results.

Greg Aldrich, product marketing director of Mentor Graphics' DFT division (www.mentor.com/dft), says that his firm's FastScan ATPG tool offers "diagnostics solutions that allow users to determine where an internal circuit problem is located based on the failure log from the tester. This will play an even more critical role as past techniques for silicon debug and failure analysis become impractical for nanometer technologies." He says Mentor now offers diagnostics capabilities for its TestKompress tool that will allow users to isolate failures internal to a chip based on compressed test responses without needing additional patterns, and that will also allow them to debug those failures without the need for special bypass or diagnostics modes.

Ravi Apte, senior VP for strategy and business development at SynTest Technologies (www.syntest.com), sees BIST as the ultimate solution but says customers are hesitant to adopt it, fearing silicon overhead and the disturbance to sensitive on-chip clock signals that BIST circuitry might impose. Such fears are unfounded, he says, but will fade only gradually. Healy at LogicVision cites another customer concern: BIST tools are hard to use. He comments that customer training as well as the rules checker available with LogicVision's products combine to overcome the difficulties that once accompanied the insertion of LogicVision microtesters into a design.

Meanwhile, SynTest has worked with Magma Design Automation (www.magma-da.com) to integrate DFT tools into a complete RTL-to-GDSII design flow. The project, under the auspices of the MagmaTies partner program, involved integrating SynTest's DFT-PRO Plus software with Magma Blast Create and Blast Fusion software. DFT-Pro Plus includes scan-synthesis, ATPG, and memory BIST capabilities; Blast Create converts RTL code to placed gates; and Blast Fusion converts a netlist to GDSII. Combining the tools at the RT level, says Apte, allows the Magma tools to inherently compensate for timing and other discrepancies that DFT insertion at the gate level could impose.

Aldrich is less optimistic about logic BIST: "So far, the market has not embraced this technology wholeheartedly, and it seems to be relegated to a niche market segment that requires a completely vectorless solution. For manufacturing test, the market seems to be staying with a deterministic ATPG approach supplemented with embedded compression techniques that are built around an embedded deterministic test approach."

Magma's cooperation with SynTest and its signing of an agreement to purchase Mojave, a vendor of design-for-manufacture (DFM) technology, highlight the emphasis that the EDA company is now placing on DFT and DFM. "Both DFT and DFM are important aspects of chip design," says Yatin Trevidi, Magma's director of product marketing. He adds that DFT and DFM affect various decisions made in the design implementation process and that they can't be effectively applied as an afterthought or as a stand-alone solution.

"Traditional DFT is totally mainstream now," says David Hsu, director of marketing for test-automation products at Synopsys. He notes that EDA synthesis vendors Cadence Design Systems (www.cadence.com) and Magma Design Automation have integrated DFT functionality into their design flows.

Current DFT efforts, Hsu says, center on the delay fault models that become critical below 130 nm, which he calls a significant customer pain point. He says his firm's TetraMAX ATPG tool permits delay tests, if a target production tester has sufficient memory to accommodate the test vectors. Meanwhile, DFT firms including Syntest as well as the DFT divisions of EDA companies including Cadence, Mentor Graphics, and Synopsys have introduced deterministic test-vector compression techniques to minimize test's impact on tester time and memory capacity.

As evidence of success in this area, Toshiba has used Synopsys' Galaxy Design Platform, which includes the company's DFT Compiler SoCBIST and TetraMAX, to design 130-nm devices. "We partnered with Synopsys on our DFT flow, and DFT Compiler SoCBIST enabled us to reduce tester time for our upcoming LSI design by 12 times and test data volume by 900 times as compared to traditional methodologies," reports Seiichi Nishio, Toshiba's senior manager for design methodology.

Aldrich at Mentor Graphics agrees that traditional scan-based DFT is mature: "ATPG is fairly mainstream for manufacturing test, but there is still plenty of room for significant innovation," particularly in the area of embedded compression. "One big difference between the introduction of scan and ATPG and embedded compression is the rate of adoption within the industry," he says. "While scan and ATPG took more than 20 years to become mainstream in manufacturing test, embedded compression, in just a few years, is already showing signs of becoming a standard for nanometer design. As embedded deterministic ATPG moves into the mainstream, a new wave of innovation around this technology will emerge. With the ability to compress test data volume and test time by 100 times or more, embedded test will trigger significant innovation in the area of test quality, which will be critical for nanometer technologies."

What does DFT mean for testers? According to Trevidi at Magma, "ATE will focus more on I/O, mixed-signal, and RF testing." He says that test equipment, focusing on high-volume, complex, yet low-cost consumer products like cell-phone chips, will act more as a system tester, performing tests on, for example, high-speed serial links, leaving memory and random-logic test to on-chip DFT techniques.

As for DFT-focused testers, he sees the same customer resistance that LogicVision's Healy reports with respect to giving up legacy systems: "Customers are asking to leverage their investment in existing 'big iron' testers" in lieu of making new capital investments in a new DFT tester, despite the latter's lower sticker prices. "As a result, it will take longer for the adoption of structural DFT testers than what was originally thought."

Figure 2. Tools such as FlopPlot can help identify defects based on test-system failure data. Courtesy of Inovys.

Al Crouch, Inovys chief scientist, elaborates, explaining that a DFT-focused architecture with large and flexible vector and capture memory will be necessary to handle test of nanometer devices, particularly at-speed AC tests: "If ATPG can make the vectors for AC scan, we can apply them—and we specifically have AC-scan modes built into the tester for launch-on-capture and launch-on-latch-shift" AC test modes.

One benefit of BIST, Burlison says, is that it can continue to function in system-level test, and that, he predicts, will be an increasingly predominant role of BIST for many companies. "People talk about getting rid of the IC tester," he says, "and there's really a big benefit of getting rid of tester when you put a device on a board or when the target product reaches the field." Aldrich at Mentor Graphics concurs: Logic BIST will serve "primarily applications that require some level of in-system test capability."

Concludes Burlison, the argument that BIST is necessary for in-system test is "an argument that BIST proponents have that will be irrefutable." To that end, he questions whether the primary customer for BIST will be the final customer instead of the design or even test engineer.