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Tabletop testers: From prototype to production?

Compact systems handle manufacturing chores and engineering debug for SOC and flash devices.

Rick Nelson, Chief Editor -- Test & Measurement World, 9/1/2004

Targeting mixed-signal SOCs, the DX shares the Fusion architecture of its floor-standing Fusion HFi and Fusion CX siblings. Courtesy of LTX.

Desktop semiconductor test systems have made inroads as laboratory tools for debugging first silicon for system-on-chip (SOC) devices. In addition, compact testers are serving as convenient platforms for test-program development for SOCs as well as flash devices, and one recently introduced system places the tabletop form factor squarely in the mixed-signal production environment.

Tabletop systems range from laptop-sized engineering debug tools to tabletop or desk-side testers for mixed-signal SOCs or flash-memory devices. The most compact systems include Intellitech's Nebula and Teseda's V500 Series systems, which target engineering debug chores. The Inovys personal Ocelot targets debug as well as production test chores for digital devices, and the LTX Fusion DX handles the same tasks for mixed-signal chips. In addition, several vendors offer laboratory systems for flash-memory test-program development.

Nebula, whose price starts at $50,000 for the hardware and software, targets the first-silicon validation of a chip design's DFT infrastructure and automatic test pattern generator (ATPG) patterns; it incorporates gate- and net-level diagnostic support for Synopsys's TetraMAX and Cadence Design Systems' Encounter Test. It requires minimal I/O pins, connecting to a DUT via a standard interface such as the IEEE 1149.1 Test Access Port. (Another desktop system that relies on minimal I/O pins is LogicVision's Validator, although Validator works only with devices incorporating LogicVision's embedded-test technology.)

During test execution, according to C.J. Clark, Intellitech president and CEO, Nebula's architecture enables "complex decision-making that is not possible with memory-behind-pin tester architectures. For instance, Nebula can apply test patterns and, based on a failure that occurs, program an onchip nonvolatile memory with the data needed to disable the faulty area and enable a redundant logic area."

Another key feature, Clark says, is Nebula's support for in situ debug of ICs soldered to boards or embedded in complete systems. The system includes software support for the external instruments—including PXI, VXI, and GPIB versions—necessary to provide source and measurement capabilities for other board and system circuitry.

The WorkBench software tool combines with the V520 test system to provide a bidirectional link between design and test data. Courtesy of Teseda.
Teseda's system is a digital-only memory-behind-pin tester that also squarely targets the lab bench—or an engineer's home dining-room table. It offers software support—in the form of its Teseda WorkBench DFT Intelligent software—for debug of first silicon. Dedicated to the test of digital chips employing scan-based designs, the V500 and WorkBench combination employs the IEEE 1450 STIL (Standard Test Interface Language) format to help bidirectionally link design and test data to help engineers locate physical faults or bad test vectors based on tester responses to test patterns generated by ATPG tools such as TetraMAX and Mentor Graphics' FastScan.

Teseda in June announced new hardware and software options that extend the V500's flexibility as an engineering tool. First, the company began offering its Teseda WorkBench software independent of the company's V500 DFT Optimized test hardware, so designers working off-line can perform debug based on previously acquired test data. In addition, the company introduced per-pin timing on the 300 pins of its new V520 platform, and it has added a fast-looping function to enhance failure analysis. A WorkBench license and a V520 system cost $35,000 each; the combination costs $65,000.

The laptop-sized V520 squarely targets the engineering desktop; the company has no plans to scale up the V500 Series for high-volume test or to introduce a floor-standing companion. To that end, Teseda has pursued relationships with traditional ATE vendors, and in February announced a link that ensures transportability of DFT design and test data between Teseda's engineering platform and Agilent Technologies' 93000 SOC production test system.

Agilent and Teseda verified STIL transportability between the Agilent 93000 and the Teseda V500 using pattern files created by ATPGs from DFT tool vendors Cadence Design Systems, Mentor Graphics, Synopsys, and SynTest. The Agilent 93000 can read pattern edits made in the V500 environment. Although a standard, STIL does not afford complete transparency between the V500 and 93000, mainly because of differences between the two platforms with respect to signal timing and accuracy, the number of precision clock drivers, achievable cycle times, and pin count (Ref. 1).

Inovys, too, supports a design-to-test link through STIL support, and its table-top-sized Personal Ocelot can serve in laboratory debugging tasks. The company offers software tools such as its FlopPlot package to support design debug.

But Inovys is also directly targeting the production floor, and its Personal Ocelot can serve not only as a debug and failure-analysis tool but also as a test-program development station for a production test system. In fact, the Personal Ocelot itself can interface with a prober or handler to serve in multisite production-test applications for relatively low-pin-count devices.

The Personal Ocelot can provide test capabilities for devices with 256 scan I/O pins, or any mix of up to 256 clock and data pins. Options for the 50-MHz Personal Ocelot include 400-MHz clock channels, parametric-measurement units, extended real-time data-capture memory, frequency-measurement capability, multiple programmable device power supplies, and an analog-converter test function.

Despite its production-test capabilities, the Personal Ocelot in general serves as a laboratory counterpart to a production ATE system. Inovys president Paul Sakamoto says he hopes the production system will be Inovys's floor-standing Ocelot, but he says he's seen interest in the Personal Ocelot as a companion to competitors' production ATE systems. An advantage to teaming the desk and floor Ocelots stems from the compatibility of both systems with Inovys's Stylus operating system, which is based on STIL; any test program developed on the Personal Ocelot can be adapted for multisite tests on the 1500-pin floor-standing Ocelot.

Mixed signal

Moving beyond the digital arena is the Fusion DX. With Fusion DX, LTX has configured its mixed-signal Fusion architecture—which powers the company's high-end Fusion HFi and lower-cost yet still floor-standing Fusion CX—into a compact tabletop unit capable of production test, albeit for low-pin-count devices. It can also serve for design validation.

The DX, formally introduced in June, is already installed at customer sites that run volume production in both wafer-sort and final-test applications, according to Neil Kelly, LTX chief technology officer. In production, Fusion DX offers the same performance and throughput for low- to mid-pin-count devices as the Fusion CX.

The Fusion DX's size can enable it to serve as a zero-footprint test system when integrated into other equipment, such as probers or handlers. The DX includes digital test capabilities, an array of DSP instruments, and a broad line of voltage and current source-measurement instruments—the same ones used in the CX version, including ones capable of Serdes test to 3 GHz. The DX has eight slots to accommodate the instruments; the CX has 20.

Kelly notes that in addition to serving as an engineering development platform or a production test system, the DX can serve as an add-on to legacy LTX systems, extending their useful lives. The DX supports up to 64 digital pins; a few mouse clicks can adapt a DX test program (written in the enVision software common to all Fusion platforms) to run in a multisite configuration on a CX machine.

Flash in the lab

SOCs aren't the only devices supported by tabletop test systems. You can find compact desktop testers for flash devices as well. Advantest, Agilent Technologies, and Credence Systems all offer desktop or desk-side flash programmers that complement their firms' full-blown, floor-standing production flash-memory test platforms, and Nextest seems positioned to introduce one as well.

Thomas Trexler, Credence director of marketing, sees his firm's desktop Personal Kalos 2 teaming up with the production Kalos 2 system to capture a substantial portion of a market growing at a bit-per-year growth rate that he puts at 50%.

Gary Fleeman, director of product engineering for Advantest's US subsidiary, notes that Advantest offers an ETS (Engineering Test Station) version of its T5771 flash-memory tester. The 0.5-m2-footprint ETS serves development tasks and "seeds the market" for its larger sibling, Fleeman says.

A comparively large floor-standing enclosure permits the use of a quiet fan in the water-cooled Versatest V5000. Courtesy of Agilent Technologies.
How compact should such a tester be? Agilent's Versatest V5000 memory tester could fit on a desk but wouldn't leave much room for anything else. According to Gayn Erickson, marketing manager at Agilent's California Semiconductor Test Division, much of the V5000's enclosure contains space that could have been squeezed out to form a more compact system.

But Agilent engineers decided the desktop wasn't the ideal location for the V5000. Had they crammed the system into a desktop format, Erickson says, the relatively small and noisy fan of the tester's self-contained liquid-cooling unit would have been at ear level. Opting for a larger under-the-desk enclosure, he says, permitted the use of a larger, quieter fan. Furthermore, he says, the engineers included an adjustment that lets you tune the fan to emit a pleasing, or at least less annoying, pitch.

FOR MORE INFORMATION

For contact information for the test vendors mentioned in this article, see our July 2004 Buyer's Guide, or consult our online buyer's guide at www.tmworld.com/bg.


REFERENCE
  1. "Transporting STIL between the Teseda V500 and the Agilent 93000 SOC Tester," Application Note AP-0005, Teseda and Agilent Technologies, 2004. www.teseda.com/pdfs/V500_93K_transport.pdf.

For more information about semiconductor test, visit www.tmworld.com/ic
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