Design for testability—a boundary-scan primer
Holger Göpel, Chief Executive Director, GÖPEL electronic -- Test & Measurement World, 10/1/2004
| Download the complete version of this article, "A boundary-scan primer." |
Test technologies that can help detect faults in PCBs include in-circuit-test (ICT), flying-probe test (FPT),
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| Boundary scan provides ICT-like capabilities without requiring expensive, complex fixtures like this one. |
For a digital assembly in which each digital circuit is detachable into sequential and combinatorial circuit parts, the minimum number of test vectors for a 100% functional test is
Q = 2(x+y) where x equals the number of inputs and y equals the number of storage elements (sequential circuit parts). For a circuit with 25 inputs (x) and 50 internal latches (y), a test rate of 100 ns per test step would require a test time of 107 years.
You can avoid lengthy test times by using "test friendly" design methods—in particular, scan-path methods, which involve interconnecting the internal storage elements into shift registers, so that circuits with sequential storage elements can be subdivided into observable and controllable combinatorial parts.
The classic among these methods is the LSSD (Level Sensitive Scan Design), which IBM developed in the 1960s for mainframe computers. Design-for-test methods like LSSD have their roots in IC technology, but they also apply to PCBs in the form of boundary scan, as defined in the IEEE 1149.1 standard. Essentially ICT without physical contact, boundary scan makes use of core logic, contact points, and some boundary-scan-specific logic implemented in an IC.
To learn more about the tradeoffs among ICT, FPT, AOI, and boundary scan, and to learn how to apply ad hoc and structured design techniques to develop assemblies that boundary scan can support from prototype to field service, see the complete version of this article at www.tmworld.com/bscan.
