Smart test for nanometer designs

Broadside patterns involve loading scan cells to produce both an initial value at the start of a path and an opposite value ready to propagate through the path. Figure 1 shows a scan-chain load sequence during which an initial value of 1 is loaded into the scan cell (labeled B) near the middle of the diagram. During the same scan-chain load, the opposite value is applied at the D input of the scan cell B flip-flop, or latch. In this case a 0 is loaded into A. Consequently, when the circuit is placed into functional mode, the tester can apply two successive at-speed clock pulses to verify the logic in the path between scan cells B and C.

For this example, the first functional-mode clock pulse will cause cell B to capture the 0 value, launching a 1 to 0 transition down the path from B to C. By the second clock pulse, the transition should have reached cell C, which should capture the 0. Failure to do so indicates a timing defect. The clocks used in the broadside scan test are pulsed when the circuit is in the functional mode—that is, when the scan-enable signal SE in Figure 2 is low. Scan-chain loading occurs prior to the application of the at-speed clocks and need not take place at functional-clock speeds.

Figure 2.  Broadside clock pulses are used during at-speed scan testing. The at-speed launch and capture pulses cause a transition to propagate and capture it at the end of a path. The scan chain loading can occur at a much lower frequency.

You could also apply at-speed clocking by using the last shift of the scan-chain load to initiate the at-speed transition. Launch-off-shift patterns are easier for ATPG tools to generate, but they require that scan-enable and shift operations meet the circuit-critical timing. In addition, timing failures in the scan chain can cause the circuit to fail the test and unnecessarily increase yield loss. As a result, most companies avoid the use of launch-off-shift patterns.

When testers are used to supply the at-speed clock pulses, there can be variations between the tester clocks and the device's internal phase-locked-loop (PLL) clocking (Figure 3). Some companies have started to use transition fault patterns using accurate PLL clocking to address the timing defects in the logic portion of nanometer devices.

One solution is to have ATPG tools use the PLL to provide the at-speed clock pulses. The clock gating and control logic of the PLL must be able to generate the desired clock pulse sequences. The ATPG tools then only need a "named capture procedure" description of what external cycles are necessary to cause the desired internal clocks to pulse (Ref. 3).

ATPG tools will automatically decide which clock pulse sequences are necessary to detect the targeted faults. The internal clock pulses are transformed into the appropriate external cycles defined in the named capture procedure.

Some test-mode and clock-gating control designs are complex and require many bits and cycles to set up. Named capture procedures can ease this difficulty by using "conditions" that must be initialized for the clocking to occur. The internal condition values required for the named capture procedure are defined. Then, the ATPG tool will load scan cells to produce the condition values when the corresponding named capture procedure is to be used. Often, the named capture procedure loads clock gating decoders or sequential gating registers.

If you supplement the stuck-at and at-speed scan patterns with additional patterns, you can improve test quality but you'll also greatly increase the number of test patterns and the required test time—possibly beyond the capabilities of your existing test equipment. For example, broadside transition scan patterns are typically three to five times larger than the stuck-at pattern set. Test resource capacity would need to grow at least as much to support the stuck-at and new at-speed patterns. Other fault models that are on the horizon, such as the multiple-detect fault model (Ref. 4), will also require an increase in test resources

Embedded deterministic test (EDT) offers an answer to this problem. EDT enables scan patterns to increase by up to 100x without sacrificing test time or test data volume (Ref. 5). It inserts compression logic only around the device's scan chain I/O. Using EDT does not necessitate any special design requirements (such as handling X-states) or logic changes to the core design. Testers behave as if they are running scan patterns without any compression logic. Even EDT diagnostics can be performed directly from the compressed responses without special test modes or additional patterns.

EDT supports all fault models and pattern types that are possible with standard scan, and it enables companies to apply all the at-speed patterns needed and any set of additional patterns for nanometer devices without increasing their test costs.