DFT with a manufacturing emphasis
An exclusive interview with a technical leader
Staff -- Test & Measurement World, 11/1/2004
| Read the continuation of this interview. |
T&MW: How does Cadence's approach to DFT differ from that of other EDA companies?
 |
| Paul Estrada, General Manager and Corporate VP of Cadence Design Systems, San Jose, CA. |
Estrada: Basically, our competitors have EDA engineers creating test tools, and test tends to be an abstract concept for them. In contrast, engineers who are very manufacturing-oriented and very concerned with the reality of parts failing on the factory floor developed the test technology we acquired from IBM. We have test guys creating EDA tools. That's a pretty fundamental distinction.
T&MW: What are the prospects for using production-test results to optimize processes in real time?
Estrada: That depends on your definition of real time. Customers are already using our Encounter Diagnostics technology to sample and analyze failures in their automated yield learning environment in manufacturing. Engineers are still involved, using the results of the analysis to adjust the process or identify the design issues. Process adjustments could occur in a matter of hours, while design issues could take weeks or months to resolve.
T&MW: What are the prospects for mixed-signal DFT?
Estrada: One of these days, someone will crack this nut. I like to think that we're going to have an inherent advantage because we are a very strong player in analog and mixed-signal EDA. Also, our Cadence Design Foundry does a lot of mixed-signal design, and people there have a lot of great knowledge in this area. But I don't anticipate an immediate breakthrough. Progress will be incremental.
T&MW: Will deterministic ATPG-based DFT approaches increasingly be replaced by pseudorandom BIST approaches?
Estrada: Memory BIST is here to stay, but logic BIST is always just around the next corner. Benefits claimed for LBIST have been that it provides at-speed test with minimal requirements, but we've addressed those concerns with transition-test capabilities and compression. In fact, we believe that faster-than-at-speed test is necessary for noncritical paths, and our True-Time delay-test tool enables that. LBIST doesn't.
T&MW: In an EDA company, is DFT a profitable product line, or is it something that must be offered to accompany the design tools?
Estrada: It's my job is to make sure it's a profit center.
T&MW: The theme of this year's ITC was "Testing from Fab to Field." What can an EDA company bring to field test?
Estrada: LBIST, MBIST, boundary scan, and the ability to implement delay test with an on-product clock are some examples, and customers might use our tools to build a test logic within a chip within a SIP. But so much goes on at the board- and system-design level that 90% of the effort required to implement field test remains with the customer. The customer still has to carry that gorilla.
See more Q&A about DFM, DFY, and the role of foundries, IDMs, fabless companies, and tester makers.
| Paul Estrada, the general manager of the Cadence Encounter Test business unit, also serves as the corporate VP of strategy for the company's design and verification division. Estrada's previous EDA experience includes co-founding 0-In Design Automation, where he was VP of verification engineering and marketing, and running synthesis marketing at Synopsys. He holds a BS in general engineering from the University of Illinois and an MS in mechanical engineering from Stanford University. |
