DSM fault models

A key goal in manufacturing test is to maximize the quality of parts delivered to customers—ideally, shipping zero defective parts while reducing the cost of testing those parts. The arrival of deep-submicron (DSM) designs has created new problems in clock skew and power delivery, while the latest nanometer technologies have demonstrated that defects are located predominantly in routing. Failure analysis conducted by major silicon manufacturers reveals that most of part failures are timing related, and delay is the biggest culprit.

Today, two approaches to bridging-fault detection are in mainstream use. The N-detect approach uses traditional stuck-at models in conjunction with enhanced ATPG algorithms to detect the same fault multiple times. In this approach, ATPG makes random decisions to target faults that reside in the least observed locations of the circuit, such that a fault is marked as detected and dropped from the target fault list once it has been detected a specified (N) number of times.

Some experiments have demonstrated (Ref. 1) that multiple-detect test patterns with high coverage not only provide a high diagnostic resolution but also can help maximize the coverage of node-to-node bridging defects. This approach makes the ATPG process more difficult and CPU-intensive, but it is conceptually easy to apply and does not require any change in the test-pattern-generation flow.

Yet, the N-detect approach is not truly deterministic: It relies on the probabilistic assumption that node-to-node bridging faults can be detected by increasing the number of times the same stuck-at fault is observed by a larger test set.

The second, fully deterministic, approach takes advantage of an improved fault model that logically describes a bridging defect; the ATPG tool can use this fault model for creating test patterns. Although this approach requires modeling efforts and a link to the physical layout for realistic fault-list creation, the generated test patterns ensure detection of defective parts that may not be caught by a high-coverage stuck-at vector set alone.

Figure 1. A bridging fault is activated when the two nets that a bridge resistance connects are driven to opposite values.

The first, the bridging fault model, assumes that two nets are contaminated by a resistive short between them, which could be caused by a piece of metal from the sputtering process. For most fabrication processes, defects between metal lines are the most likely defect mechanism.

Whereas the stuck-at fault model assumes that a cell input or output is always tied to a fixed value, the bridging fault model assumes that one net will dominate the value driven on the other net via the electrical path through the resistive short. If one net dominates, then the other may have an incorrect logic value at one or more of its fanouts. The dominant net is commonly referred to as the aggressor, and the corrupted net is called the victim (Figure 1).

The bridging fault model can be described in terms of the stuck-at fault model, with two additional conditions:

• the aggressor must be at the opposite value of the victim, and
• four possible bridging faults exist for each pair of susceptible nets.

Each net can have two possible values and might behave as either the aggressor or the victim. An important conclusion that can be drawn from the relationship of these two fault models is that if a bridging victim is successfully tested, the associated stuck-at fault at that location will be automatically tested as well. In other words, a stuck-at fault is just a special case of a bridging fault, where the aggressor is a net that is always at a fixed value. This obvious property has one profound benefit: It is not necessary to generate and run two independent test sets for stuck-at faults and bridging faults. A high-coverage bridging fault test set will also provide high coverage of stuck-at faults.

The second type of deterministic fault model is the transition fault model. While this fault model has been in limited use for many years, the more common occurrence of resistive vias at 130 nm has lead most major semiconductor vendors to require high-coverage transition testing over the past several years.

The transition fault model assumes that a cell input or output has a defect that does not allow a logic transition to propagate through the cell or along the net within the time required for proper device operation. In general, transition faults occur at the same sites as stuck-at faults, although they may be ignored on signals such as asynchronous resets or test modes, which are not expected to operate at-speed.

A transition fault is an extension of a stuck-at fault on the same node, with two additional conditions:

• the node must undergo a transition to the fault-free value, and
• the final value of this transition must propagate to an observation point (typically a scan cell) within a time that corresponds to the at-speed operation of the device.

As with the bridging fault model, once a transition fault has been detected, its corresponding stuck-at fault is guaranteed to be tested.

The third deterministic fault model is the path-delay fault model. Where the transition fault model assumes that the additional delay from a defect is relatively large and localized to a single point, the path-delay fault model assumes that delays may be distributed across multiple gates or even the entire device. The path-delay model addresses the specific goal of testing all the accumulated delay—both expected and from any defects—along critical timing paths of the design.

While the path-delay fault model is much more complex than the other two, which only involve one or two circuit nodes, there are still important relationships that can be exploited to improve the efficiency of testing for multiple fault models. The most important of those is that a robust path-delay test guarantees detection of all the transition faults along that path, and that a non-robust path-delay test will often lead to the detection of many transition faults along a path. Also, just as tests for bridging and transition faults uncover the related stuck-at faults, tests for path-delay faults also detect all or many of the corresponding stuck-at faults.

Finding the optimal DSM test is an NP-complete problem, as it would make full use of all the fault models in order to capture all defects. Instead, near-optimal results can be achieved with this proposed workflow (Figure 2):

• generate patterns for the "most complex" fault model;
• fault-grade those patterns against the "next-most-complex" fault model;
• generate additional patterns on that fault model to improve, or "top off" coverage; and
• repeat this for each subsequently "simpler" fault model.

Figure 2. An optimal DSM testing flow generates test patterns, grades those patterns, generates additional patterns, and repeats for each fault model.	Figure 3. This flow for bridging-fault extraction based on electrical analysis can generate an accurate node file but forces RC extraction to be re-run.

Bridging pairs based on electrical analysis

Extracting physical defects based on electrical analysis can uncover all bridging pairs, as it allows generation of a node file for ATPG, where circuit net pairs are listed on the basis of their coupling capacitance. But a

A potential solution is to further refine the technology file for a given process. Changes can be applied to adjust the dielectric values so they more closely correlate with bridging defect probability, either decreasing the weight for inter-layer net pairs or increasing it some order of magnitude for intra-layer couples, or both.

This approach (Figure 3) allows semiconductor manufacturers to generate a more accurate node file, which better orders and prioritizes net pairs that are more exposed to a bridging defect, but it also forces the manufacturer to rerun the RC extraction. Also, the technology file—which is typically proprietary to a foundry—must be modified, and that may prove undesirable.

Figure 4. High coupling capacitance does not necessarily lead to high bridging probability. Although the capacitances for pairs (n1, n2) and (n3, n4) are the same, the (n3, n4) pair is much more likely to experience a bridging fault.

Figure 5. A flow for bridging-defect extraction based on a topological approach is an effective alternative to electrical-based defect-extraction techniques.

The experimental bridging defect extraction based on a topological approach relies on the following principles:

• only intra-layer bridging candidates are examined, and
• only net pairs facing each other at the minimum spacing, as defined by the technology rules, are computed.

For conductors that run adjacent to each other on multiple metal layers, the cumulative facing length is calculated, thus providing an accurate classification of the bridging probability. Although this approach requires multiple data analyses and the availability of the accurate design rules, it should result in a more accurate and manageable node file for ATPG of bridging faults. Indeed, our results from this approach, summarized in Table 1, demonstrate that combining models for bridging, transition and stuck-at faults in an IC design flow enables optimal test coverage. T&MW