News Briefs

Agilent Technologies has introduced Agilent InstaPin for its 93000 SOC Series test system, a program to offer per-pin licenses that can be shared among pins of one card, one tester, and multiple testers, whether located in a single facility or deployed worldwide. With the InstaPin program, testers can be software-configured instantly to match specific DUT requirements. Because no hardware is moved, there is no need to recalibrate and risk hardware damage or experience downtime between tests.

The InstaPin program applies only to Pin Scale series 93000 cards, including the Pin Scale 800 (introduced in March), which offers 200- to 800-Mbps performance, with prices starting at $600 per pin. Since the per-pin licenses float between pins in a test head, InstaPin enables instant sharing of the Pin Scale digital cards' features (memory and speed).

Manufacturers can buy only the capabilities they need to match testing requirements on a pin-by-pin basis. If a test requires two differential pins at 2.5 Gbps for PCI Express, a license needs to be purchased for only two pins, not the whole card. When test requirements change, the tester can be upgraded using software licenses.

Individual per-pin licenses are priced between $180 and $1000, and are available now for users of Agilent 93000 Pin Scale digital cards. www.agilent.com/see/instapin.

Cadence Design Systems has announced Cadence Encounter Test Architect, a full-chip test architecture development technology that includes a unified compiler-based methodology for full-chip test to provide for faster development of a higher-quality test infrastructure than is currently possible with point test tools.

Based on a test infrastructure compiler, Encounter Test Architect supports a unified methodology for specifying, compiling, and verifying full-chip test. This includes scan, compression, memory BIST, on-product clock generation, boundary scan, and I/O test.

To create the necessary full-chip test today, test teams separately specify, implement, and verify each structural

element—typically with different tools—and manually create the test infrastructure that ties everything together. This process can lead to silicon redesigns, poorer product quality, and a high cost of test.

Encounter Test Architect's methodology is based on test infrastructure compilation. Test engineers use the product's unified environment to specify, compile, and verify full-chip test capabilities, including the individual test structures and the hierarchical (or flat) test infrastructure. The Encounter Test Architect infrastructure compiler includes a memory BIST capability with high fault coverage, easy BIST engine sharing, and automatic insertion and connection across the design hierarchy. The Encounter Test Architect team worked closely with ARM to develop and validate the memory BIST solution. This ensured product interoperability and Encounter Test Architect's support of all ARM-recommended test algorithms. Encounter Test Architect will be available for shipment at the end of April. www.cadence.com.

On February 22, at a ceremony held during the 2005 APEX conference in Anaheim, CA, Test & Measurement World honored the recipients of our annual test industry awards. Publisher Russ Pratt presided over the ceremony and began the evening by recognizing the 12 products that won a 2005 Best in Test Award. Rick Nelson,T&MW's chief editor, presented an award plaque to a representative of each product's manufacturer.

Pratt then announced which of the 12 products had been selected the 2005 Test Product of the Year by T&MW's readers: the WaveSurfer oscilloscope from LeCroy. The WaveSurfer is especially notable for its unusual dimensions: Its 10.4-in. display fits into a box that is only 6-in. deep. In addition, the scope captures 250,000 samples on four channels. Dr. Mike Lauterbach, director of product management for LeCroy, accepted the Test Product of the Year award plaque from Nelson.

Next, Nelson addressed the crowd to introduce the Test Engineer of the Year. This year, our readers selected Anthony Levandowski, to receive the honor. Levandowski, who is based at Berkeley, is building a motorcycle that will compete in the 2005 DARPA Grand Challenge, a competition that requires autonomous vehicles to traverse up to 175 miles of terrain in the southwestern US in less than 10 hours. Our readers selected Levandowski from a group of six nominees who we announced in our September 2004 issue. As part of his award, Levandowski will designate an engineering school to receive a $20,000 education grant, courtesy of National Instruments, the award sponsor.

To conclude the evening, Nelson introduced a new industry award: the Test of Time Award. Created to recognize product lines that provide state-of-the-art performance for at least five years after their introduction, the inaugural award was presented to the 93000 SOC Tester from Agilent Technologies. The 93K debuted in 1999 and has continued to evolve to provide high-performance analog and high-speed serial I/O test capabilities. Jack Trautman, president of the Automated Test Group at Agilent, accepted the award from Nelson.

For complete information about the Best in Test Awards program and for profiles of this year's winners, go to www.tmworld.com/bit.

Pursuing the industry's highest image resolution for 3-D automated x-ray inspection, Teradyne has announced its ClearVue 3-D x-ray off-center tomosynthesis imaging technology. Designed for detecting solder defects and production flaws on densely packed boards that use BGA-style components, ClearVue operates using a stationary x-ray source and detector and does not require complex or rotating mechanical parts.

The company expects the technology to provide lower false-call rates (offering up to a 40-fold improvement), improved reliability, better repeatability, and faster cycle times when compared with laminography and other 3-D x-ray techniques. The company expects to debut its first ClearVue system in May. www.teradyne.com.

LeCroy has entered the sampling scope market and has taken the bandwidth lead. The WaveExpert 9000 sampling scope and SDA 100G serial data analyzer boast a 100-GHz bandwidth with a 10-Msample/s sampling rate. The SDA 100G comes standard with jitter-analysis software that's optional on the WaveExpert 9000. Both instruments come with a set of compliance masks for popular serial data streams.

LeCroy's sampling scopes also feature 4 Msamples of waveform memory standard with optional memory to 512 Msamples. Both scopes are mainframes with electrical or optical input modules available. Four electrical modules offer bandwidths of 30 GHz, 50 GHz, 70 GHz, and 100 GHz. Optical modules cover 25 GHz and 50 GHz. A 25-GHz TDR module is also available.

Prices: WaveExpert 9000—$21,500; SDA 100 G—$41,500. Input modules range from $7000 to $50,000. LeCroy, www.lecroy.com.

Yokogawa's DL9000 scopes combine small size with wide bandwidth and an ability to adjust sampling rate and waveform memory. The portable scopes claim bandwidth of 1.5 GHz and 1 GHz with maximum sample rates of 10 Gsamples/s and 5 Gsamples/s, respectively.

The DL9000 scopes are available with 2.5 Msamples of waveform memory on each of four channels, with an "L" version containing 6.25 Msamples on each channel. On the DL9000, you can select the number of acquisitions that the instrument sends to the 8.4-in. screen in each second, and you can also select the best acquisition rate, sample rate, and memory for your application.

In accumulate mode, the scope overlays each acquisition on the screen. It can store the 2000 most recent screens (at 2.5 ksamples per acquisition) and you can scroll through them to look for signal peculiarities. The scopes have an array of analysis functions that include mask tests and eye-pattern measurements such as jitter.

The scopes offer LAN and USB connectivity to host computers and provide two front-panel USB host ports. An IEEE 488 port is available through front and rear PC Card slots.

Prices start at $10,995 for 1 GHz bandwidth and $15,495 for 1.5-GHz bandwidth. Yokogawa, www.yokogawa.com/tm.

ESTECH, May 1–4, Chicago, IL. The annual technical meeting of the Institute of Environmental Sciences and Technology (IEST). www.iest.org/estech/estech.htm.

NEPCON East/Electro, May 3–5, Boston, MA. These co-located shows cover electronics manufacturing and components. Sponsored by Reed Exhibition Cos. www.nepconeast.com.

International Instrumentation Symposium, May 8–12, Knoxville, TN. A forum covering instrumentation techniques, development, and applications. Sponsored by ISA. www.isa.org/IIS.

The Vision Show West, May 17–19, San Jose, CA. A technical conference and exhibit covering machine-vision components, systems, and solutions. Sponsored by Automated Imaging Association. www.machinevisiononline.org.

Sensors Expo, June 6–9, Rosemont, IL. Topics include physical sensors, sensor networks, MEMS/nanotechnology, and wireless sensing and IT technology. Sponsored by Advanstar Technology Group. www.sensorsexpo.com.

IEEE MTT-S, June 12–17, Long Beach, CA. The Microwave Week provides research results, product announcements, and discussions of microwave techniques. Sponsored by IEEE. www.ims2005.org.

Design Automation Conference (DAC), June 13–17, Anaheim, CA. Topics include design methodologies and electronic design automation (EDA) tool developments. Sponsored by IEEE. www.dac.com.

Semicon West, July 11–15, San Francisco, CA. The show has been split into two venues during the past few years, but this year it will be reunited in one location. Sponsored by SEMI. www.semicon.org.

EMC Symposium, August 8–12, Chicago, IL. Sponsored by IEEE, EMC Society. www.emc2005.org.

To learn about other conferences, courses, and calls for papers, visit www.tmworld.com/events.