The best-laid boards
Steve Scheiber, Contributing Technical Editor -- Test & Measurement World, 4/1/2005
For many years, board designers have endured the litany of the test industry—design for testability, permit visibility to internal circuit logic, provide access, access, access. When most boards included nodes on the underside, DFT guidelines concentrated on ensuring that all of them were available for contact by a bed of nails. When circuit density and levels of integration made following that recommendation increasingly difficult, the industry came up with an alternative—boundary scan. Hailed as a panacea (at least when it could be effectively implemented), it was touted as imperative by loud voices in the industry.We should have known better. There are no panaceas. At the International Test Conference last October, a panel discussion explored a dissenting opinion—that designing a circuit with boundary scan makes even encrypted data more vulnerable to hackers and fellow travelers (Ref 1).
 |
| Encoding and decoding logic within the boundary-scan chain will prevent outside access. |
Eliminating boundary scan is not an answer. The need for test generation, adequate fault coverage and defect detection, and identification leave designers with little alternative.
So what do we do?
Rohit Kapur of Synopsys calls on designers to encode and decode logic within the scan chain to prevent anyone from exercising the circuit without the proper codes (Ref. 2). Louis Ungar, president of ATE Solutions, suggests simply stopping the boundary-scan chain short of the edge connector; he recommends that manufacturers provide a node near the edge that can be probed but cannot be accessed from within the target system.
Protecting future products from this vulnerability is imperative. Yet, design-security recommendations will not address the millions of scan-based products already in the field. Replacing them will take time for normal equipment turnover. Companies and the industry at large must explore ways to combat this type of hacking.
| References |
|
|
Asset Intertech has incorporated its ScanWorks JTAG test system into Agilent's i5000 board-test system. Agilent will bundle ScanWorks into its Medalist in-circuit test product line along with its own Interconnect Plus boundary-scan tool and Silicon Nails, which works with boundary-scan chains to test non-boundary-scan devices. Users can migrate tests from a ScanWorks station in the design lab to manufacturing, where they can merge the tests with Silicon Nails tests. 
