Technology adapts to user needs

Synopsys’s DFT Compiler MAX deploys multiplexers to enable adaptive alliances between scan inputs and scan chains.

According to Tom Newsom, VP and GM of Agilent's SOC business unit, "Each pin of the 93000 Pin Scale digital cards can be software-scaled over its memory depth and speed range, allowing test systems to be configured to match device requirements, pin by pin." If, for instance, a test requires two differential pins at 2.5 Gbps for PCI Express, a license needs to be purchased for only two pins, not the whole card. Because no hardware is moved, there is no need to recalibrate and risk hardware damage.

Yet a third example is the Synopsys DFT Compiler MAX, a DFT synthesis tool that offers one-pass test-data compression capabilities to address design and test challenges occurring in 130-nm and smaller process technologies. DFT Compiler Max, said Bijan Kiani, Synopsys VP of marketing, provides some of the features of Synopsys's SoCBIST (aimed at high-end customers) in an easy-to-use tool that meets the needs of mainstream customers who are moving from 180-nm to 130-nm designs for the first time.

All three cases did involve technical prowess: Teradyne engineers pulled off some deft engineering to fit standard FLEX cards into the microFLEX enclosure while ensuring adequate electrical and thermal performance; Agilent had to develop the Pin Scale cards that make the InstaPin program possible; and Synopsys tailored its adaptive-scan technology for use in DFT Compiler MAX (Ref. 1).

But in all three cases, it's not the gigahertz, or test-vector compression ratios, that count. As Agilent's Newsom put it, the goal is "maximum asset utilization and minimum capital expenditure" for the firms' customers.

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