Keep your eye on the metal bumps

How the wafers get their bumps

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Getting the bumps—usually solder or gold—onto wafers (Figure 1) introduces challenges that include inspecting the bumps to ensure they meet design criteria. (See, "How the wafers get their bumps") At present, three inspection technologies predominate—laser scanning and image analysis, conformal microscopy, and Moiré interferometry. Understanding their characteristics and the requirements for inspecting bumped wafers will help you decide which techniques suit your present and future needs.

A combination of inspection technologies lets systems from RVSI Inspection (Figure 2) examine bumps two ways. The first technology uses a laser-triangulation system; the second employs a line-scan camera that acquires images of a wafer's surface.

Figure 1.  A field of solder bumps on a wafer shows their relative position and size. In this case, wide spaces separate the bumps. Courtesy of August Technology.

A second scan with the camera obtains quantitative information about bump diameter and location. That scan also picks up defects such as missing bumps, misshaped bumps, mouse bites, nodules, and bump bridging. Because image analysis can cover any area on a wafer—not just bumps—the system also can look for other problems, such as etch residue, foreign materials, and holes in the passivation layer.

Figure 2.  The WS-3000 system inspects 200- and 300-mm wafers. This unit combines 3-D laser technology with a 2-D high-resolution camera to provide quantitative and qualitative inspection information. Courtesy of RVSI Inspection.

"Even though more users require 100% inspection of a wafer, they don't always inspect the height of every bump," explained Asgari. "They may scan a small sample of bumps with the laser to obtain height data and then scan the entire wafer with the camera to look for defects."

"Triangulation with a laser looks easy on paper," said Asgari, "but the system must work with a variety of surfaces, from highly reflective lead-based solder to duller lead-free solder. The hardware and the software take that sort of variation into account and continue to produce accurate information."

The system's line-scan camera relies on a time-delay integration (TDI) image sensor that transfers pixel data from one row of detectors to the next in synchronization with the wafer's motion. In this way, the sensor integrates a line scan, which increases scan rates and reduces the amount of light needed to illuminate the wafer. Like any camera, a line-scan camera produces small distortions, but algorithms can quickly correct them. An area-scan sensor, on the other hand, introduces distortions in two dimensions, which take image-analysis programs longer to compensate for.

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	Figure 3.  A rapid confocal scanning (RCS) system produces images such as these that show (a) a bump bridge, (b) a missing bump, and (c) sheared-off solder bumps. Courtesy of August Technology.

As part of an in-house study, one RCS user inspects bump heights about 10 times smaller than the dimensions noted above. "That system isn't part of the production process yet," said Roy, "but the customer plans to deploy it."

Confocal microscopy employs a point light source, usually a laser diode, and a detector that measures only a pinpoint of light. The resulting image lets the inspection system obtain depth information from features in an image. In simple terms, the system adjusts the microscope's height and focuses the image to produce a height measurement for a bump under the microscope. During an inspection pass across a wafer, for example, a confocal microscope maps x-, y-, and z-axis coordinates across each bump. The microscope also provides images of the wafer (Figure 3).

The RCS equipment also performs bump morphology, or bump-top mapping. Bumps require a surface roughness within a specific range to ensure good adhesion to another conductor. A smooth bump won't adhere to its surface, and an overly rough bump won't offer enough surface contacts for a solid bond. "Users can measure the surface roughness and also look for nodules or craters, both of which affect contact," Roy explained.

Traditionally, when engineers discuss bump inspection, they imply the need to inspect wafers after bump formation and prior to shipment. "Some customers now inspect wafers during bump processing," said Roy. "Prior to applying under-bump metallization (UBM) layers, they inspect wafers to check for any corrosion that would adversely affect metal bonding. After they apply the UBM layers, they inspect again to check the metal surface for defects." (The UBM layers provide a metal base to which the solder will adhere.)

During solder-electroplate steps, for example, process engineers can monitor wafers to ensure vias have filled with solder. If a wafer needs more solder, it can go back into a plating bath. If a wafer has too much solder, the process engineers can remove the excess. "By inspecting at several steps, you gain the opportunity to rework valuable wafers," explained Roy.

Throughput of wafers matters, too, and the goal for 2-D and 3-D bump inspection ranges from 10 to 20 wafers/hr for 200- and 300-mm wafers. "Users don't want equipment to spend more than three or four minutes inspecting a wafer," noted John Pak, product manager at August Technology.

Although the change to lead-free solder or gold bumps may affect some inspection technologies, because of surface-reflectance and bump-size differences, Pak emphasized August hasn't experienced any problems as customers change materials.

Figure 4.  Measuring slight changes in the Moiré image produced by passing a reflected grid pattern through a similar pattern provides geometric information about metal bumps on a wafer.

Users also face challenges as bumps get smaller. "Engineers design IC packages that require 50–90-micron bump diameters, and they put the bumps closer together," said Clay. "We see side-to-side spacing down to about 50 microns." The same sorts of dimension reductions take place for gold bumps. Today, 15–17-μm-tall gold bumps are typical, although Clay reported some manufacturers plan to deploy products with 5-μm-tall gold bumps. Gold-bump spacing may range from 7–10 μm from side to side. Clay added, "At those dimensions, some inspection technologies reach their limit. So, equipment will find it difficult to differentiate bumps from the other 'features' on a wafer's surface."

Figure 5.  A projected grid moves slightly to scan solder bumps on a wafer. In the FMI instrument, only the projected grid moves. The camera and wafer remain stationary. Courtesy of Solvision.

Figure 6.  A false-color 3-D plot, obtained from interferometry data, shows four solder bumps. The one on the right is defective. Courtesy of Solvision.

Solvision combines Moiré interferometry with phase shifting to produce a system that simultaneously inspects solder bumps, wafer defects, and the wafer's surface. The FMI technique measures light-intensity changes as the system moves the light pattern in small increments across the surface of a wafer. "Unlike other inspection equipment, an FMI system doesn't move from bump to bump to take measurements," stressed Clay. "Instead, it measures all of the bumps in the field of view. Thus, the FMI technique makes it easy to increase the field of view so a system can inspect more bumps or features at one time."

Mathematical algorithms process the Moiré image data and yield a plot of the wafer's topography (Figure 6). The equipment's 2-D data provides information about cracks, proper fiducial alignment, the presence or absence of bumps and leads, and so on. Because the 3-D topographic information includes a height value for each pixel, algorithms can calculate solder volumes for electroplated solder and screen-printed solder prior to reflow.

August's Roy noted a growing interest in placing post-passivation layers (PPLs) on top of wafers. Designers use these layers to hold resistors, capacitors, inductors, and other components formed using large-geometry processes with feature sizes that range from 2–10 µm. Moving components to PPLs improves device performance, but the process adds from four to 20 layers. Engineers need inspection systems that will examine the PPLs and ensure they're ready to accept solder bumps. "When people buy an inspection system, they must ensure it will adapt to new technologies," said Roy.