PXI extends reach of boundary scan
Mario Berger, Göpel electronic -- Test & Measurement World, 6/1/2005
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| Fig. 1 JTAG boundary-scan outfits each pin of a digital device with test registers that can stimulate or record I/O data. |
Boundary scan was developed in the late 1980s by the Joint Test Action Group (JTAG) and was approved as IEEE 1149.1 in 1990. The basic principle (Figure 1) is that boundary-scan-compliant devices incorporate a scan register at each digital I/O pin, connected together in a chain. Each register provides an input cell that can measure the signal present on the pin, an output cell that can send a signal to the pin, and storage cells that connect to form a shift register. Connecting boundary-scan devices together extends the shift register, creating a single chain that allows access to every digital I/O pin on a circuit board.
In normal operation, signals moving on and off the chip pass through the boundary-scan cells. When in test mode, however, the registers can impose a signal on an output pin or capture a signal from an input pin—core logic and pins are basically disconnected. To load the register (boundary-scan cells), the user shifts a test vector through the scan chain with the proper logic values for the input, output, and control cells.
Triggering the test mode causes the output cells to replace a device's normal output signals at its I/O pins, and then captures the data present at the input cells. To read the results, the user shifts the vector out of the chain. The technology thus provides embedded test access to all of a circuit board's nodes that contain boundary-scan cells, reducing or eliminating the need for mechanical access through probes.
TeamworkCombining PXI with boundary scan can provide a variety of useful test options to design and test engineers. Simply running a boundary-scan test pattern under PXI system control is nothing new, though. The key to expanding the limits of plain boundary scan lies in incorporating PXI's trigger features, which allow the rest of the PXI resources to become synchronized with the boundary-scan test activity.
One example is to use the PXI and boundary-scan combination to monitor the power supply of a unit under test (UUT). When a power supply does not work properly, diagnosing its faults can often require lengthy debug sessions. With a combined PXI and boundary-scan test setup, however, a PXI card can record the supply voltage and the current values during boundary-scan test execution. Correlating these recorded values to specific boundary-scan vectors can help you diagnose events such as ground bounce and logic-induced shorts to power-supply rails on the UUT.
The combination can also extend boundary-scan test to a board's analog section. PXI modules provide the tools for the stimulation and measurement, synchronized to the boundary-scan test stimulus and response patterns. This allows verification of functional blocks such as digital-to-analog converters and analog-to-digital converters, limit comparators, and a host of other mixed-signal operations.
The combination can also enhance the performance of boundary scan in manufacturing testing. Using the parallel PXI bus to control digital I/O modules allows parallel stimulation of a UUT's peripheral connectors in sync with the boundary-scan test pattern. This permits the test software to treat UUT and I/O modules as independent units. It also bypasses the need to shift test vectors—or reduces the number of vectors—into the boundary-scan chain, resulting in faster test execution. Similarly, time-intensive boundary-scan applications such as in-system configuration of Flash devices execute much faster in this configuration.
These few examples suggest the enormous potential that lies in the combination of PXI and boundary scan. The open, modular architecture of PXI, combined with its trigger and local bus features, provides an ideal high-performance platform for enhancing the capabilities of boundary scan. With sophisticated implementations and automated software support, PXI-based boundary-scan I/O modules pave the road for new test capabilities.
| Author Information |
| Mario Berger is application engineer—boundary scan at Göpel electronic in Jena, Germany. m.berger@goepel.com. |
