Scan test drives yield

Yield enhancement has taken on added significance as IC feature sizes shrink below 90 nm, especially in the area of effective test methodologies. In fact, in the most recent version of the International Technology Roadmap for Semiconductors (ITRS; http://public.itrs.net), all of the most difficult challenges for yield enhancement are directly related to test methodologies and defect identification. Yield enhancement can basically be broken down into a three-step process:

• isolating failing devices,
• determining what caused the failure, and
• implementing corrective changes to improve yield.

Traditionally, production test has focused primarily on the first step—isolating failures—but recent advances in scan-based test have expanded production test's role to include the other two steps as well. For example, failure-diagnosis tools are determining the cause of device failures, and design-for-manufacturing (DFM) tools are focusing on implementing corrective changes.

The past 10 years have seen a dramatic shift from functional testing to scan-based test techniques that provide high fault coverage with concise metrics for gauging relative test quality. Until now, the primary focus of scan test has been to minimize test escapes—those parts that pass all manufacturing tests but end up failing in the field. Determining why the parts fail has been of secondary importance: Essentially, the scan tests have been pass/fail. To uncover possible causes of failures, semiconductor manufacturers have employed in-line inspection and failure analysis on a small subset of devices.

Devices that end up in the failure bin offer a gold mine of information, but taking time to analyze only a small sample of the failed devices delays the implementation of corrective action and leads to lost profits while your yield remains low. Scan test gives new life to defective devices by letting you analyze them as part of the test process to determine the exact cause of the failure and gain insight to yield improvement.

It is scan test's methodical nature that makes it effective for isolating defects. Because each structural element of the logic design is targeted during automatic test-pattern generation (ATPG), the tester can use failure information to find the logical location of the defective behavior. In a sense, scan-test failure-diagnosis algorithms reverse the process of ATPG to find offending logic that causes a scan test to fail.

Figure 1.  Scan-test failure diagnostics can isolate defects to logical and physical levels based on netlists, test patterns, and ATE failure data.

Unfortunately, ATE normally has a relatively small buffer for logging failure data during manufacturing test, so the information is often truncated. This lack of data puts a heavier burden on the diagnostic tool. One solution is to rerun the test off the production line, but this method can be difficult to implement because you need to replicate all of the production-line test conditions.

Failure diagnosis can be further complicated by test-vector compression techniques that make diagnosis difficult, if not impossible. Therefore, you should use a test-compression approach that permits diagnosis directly from the truncated production test failure logs, without requiring any special patterns (Ref. 1).

The output from a scan diagnostic tool is shown in Figure 2. Because individual defects can cause multiple test failures, the tool groups the defects into "symptoms." Each symptom can be caused by one or more "suspects," depending on the complexity of the failure and the amount of failure-log information collected. Using advanced diagnostic algorithms, the tool classifies the suspects into different types. As an example, a bridging defect (the symptom) between two logic signals will likely have at least two suspects—one for each side of the bridge. Likewise, an open defect could be caused by multiple suspects due to the disconnection of pins.

Figure 2.  A scan-test failure-diagnostics output report groups defects according to symptoms that may be exhibited by one or more suspects.

The report shown in Figure 2 only deals with the logical location of the suspects. To determine the location and type of the actual silicon defect, physical information must be correlated to the logical location. The physical characteristics of the failing logical locations can help determine the type of defect. For example, an investigation of the physical view can determine whether a suspected bridge in the logical domain is possible physically.

ATPG tools have typically focused on achieving the highest fault coverage with the minimum number of patterns, a practice that made sense because of the test-time and pattern-count limitations that ATE imposed. To keep the number of patterns low, pattern sets were not optimized for isolating defects in the event of test failures. Fortunately, test-pattern-compression technology now offers compression ratios up to 100X, which has eased most test-time and pattern-count concerns. Compression permits the addition of scan tests that can target particular defect types, thereby providing for more accurate failure diagnosis. Here again, the physical layout information can be used, but this time to help to optimize the test-pattern generation itself.

As an example, look again at bridging failures. To target bridges during ATPG, you can use a two-pronged approach. First, you can use the physical layout to determine which nets are most susceptible to bridges, and you can generate tests that target those bridges.

Then, because it is nearly impossible to develop rules that target all possible bridges, you can apply a second step—focused in the logical realm that augments the conventional fault models. In this, called the multiple-detect method, a traditional ATPG tool generates patterns targeting each fault multiple times in order to increase the probability of detecting nonmodeled defects without using layout information. With this method, each net is activated multiple times (Ref. 2). With other nets being set to opposite logical values, the probability of uncovering different bridges increases.

The combination of both of these steps greatly increases your likelihood of uncovering bridge defects during scan test and being able to identify the location of the bridge during failure diagnosis.

Implementing a scan-test failure-diagnosis methodology can require significant planning across multiple organizations, each using a variety of tools. To begin, the design-for-test (DFT) engineer creates the scan-pattern test sets. Then, these test-pattern sets are converted to an ATE program by a test engineer. Failure logs from the ATE must be gathered after manufacturing test. These logs need to be converted to a format readable by the scan failure-diagnosis tool. At the time of diagnosis, the tool will need to read the failure log, the logical netlist, the test patterns, and possibly the physical layout.

The coordination of all this data can span across different groups within one organization, over months or years, and can even involve different companies. Ensuring the consistency of the data during the entire process can be a significant challenge, so it is helpful if you use a diagnostic tool that can determine data consistency and assist in troubleshooting.

Putting scan-test failure diagnosis into the manufacturing flow requires efficient data collection and rapid analysis. The resulting information from diagnosis will have to be fed into larger manufacturing databases and also sent to failure-analysis equipment for subsequent deprocessing and defect isolation.

Tools are now available that extend scan test's application to failure diagnosis and analysis. These tools look at the problem from a failure-analysis (FA) engineer's point of view, thereby reducing the need for being a "DFT expert" in order to get meaningful results.

As yield improvement takes center stage, scan-test failure diagnosis is proving to be a key component for monitoring manufacturing defects and enabling rapid corrections to systematic yield loss. As the ITRS has indicated, the industry must still overcome significant challenges before this failure diagnosis is integrated into the overall process. The development of scan-failure diagnosis tools is helping manufacturers meet these challenges.