Workshop explores board test

On November 3–4, 2005, Agilent Technologies hosted the fourth annual IEEE Board Test Workshop at its facility in Fort Collins, CO. The brainchild of UK design-for-testability consultant Dr. R.G. "Ben" Bennetts, the conference explored various issues related to board test.

Five years ago—"aided and abetted by others"—Bennetts founded the Board Test Action Group, now known as the Board-Test Technical Activities Committee (BTTAC) of the IEEE Test Technology Technical Council (TTTC), to rekindle interest in board-level test at the International Test Conference. For a number of years, the ITC had concentrated primarily on device test.

Moore’s Law affects technology at both the board and the device level.

This year's sessions covered a wide range of topics. One presenter, independent consultant Bob Russell, explored z-plane deformations during flying-probe testing. He contended that resulting board warpage significantly threatens board quality and can lead to false failures.

A paper by Ken Parker from Agilent contended that Moore's Law presents no less a challenge at the board level than it does at the device level. Parker cited increasing reliance on lower operating voltages and optical signaling as high-priority concerns.

Bennetts and Agilent's Jeff Rearick presented status reports on the SJTAG and IJTAG initiatives, respectively. SJTAG looks at data languages and formats associated with boundary scan in multiboard system environments. IJTAG focuses on using the IEEE 1149.1 test access port as a common serial interface to access device-internal "instruments" for configuration, test, diagnosis, and debug. Bennetts explained, "Although the two initiatives come from opposite ends of the 'use of boundary-scan' spectrum, they may experience common problems and common solutions. So far, however, the two initiatives are proceeding down different paths."

Carlos O'Farrill, from contract-manufacturer Jabil Technical Services, offered a comparison between a low-cost in-circuit tester (manufacturing-defects analyzer) and more traditional high-end equipment. O'Farrill attempted to clarify the number of board-test failures caused by faulty devices and determine if the lower-cost machine could provide results comparable to those of its higher-priced sibling. A lively discussion ensued, centering around whether he had made a fair comparison and whether his methods could distinguish between a faulty device and a bad solder joint. Bennetts commented, "That type of interaction between the presenter and the audience adds to the intensity of the sessions." The 2006 workshop will likely take place in September, although not under Agilent's auspices. To download the 2005 presentations, visit www.dft.co.uk/BTW2005.