DFT drives yield improvement

ROBERT HUM VP & General Manager, Design Verification and Test Division, Mentor Graphics, San Jose, CA Robert Hum joined Mentor Graphics with Mentor's acquisition of IKOS Systems in 2002. Hum has more than 25 years of experience in engineering, marketing, business development, and operations. Most recently, he served as the executive VP and COO of IKOS, and he has also held senior business and technology management positions at Cadence Design Systems and Bell-Northern Research (Nortel). Hum has an MSEE from McGill University in Montreal, QC, Canada.

For more Q&A with Robert Hum, where he describes in detail Mentor's verification and test offerings and elaborates on the future of DFT, read the continuation of this interview.  Read LogicVision's response to this column on our Letters page.

T&MW: At DAC, you said that more than 50% of design is verify and test. Could you explain?

Hum: Several studies have measured how many engineering hours go into certain activities. About a third of the design activity involves translating written specs in English into RTL. The other two thirds of the time is verification. It's writing functional test benches and verifying that your design, in fact, does meets the spec and that you have correctly implemented it.

T&MW: What verification and test products does Mentor offer?

Hum: On the design-verification side, we offer ModelSim and Questa. For test, we offer FastScan ATPG and TestKompress as well as built-in self-test products for both logic and memory. We also offer a boundary-scan product called BSDArchitect.

T&MW: TestKompress was introduced in part to address vector-memory limitations on test hardware—are memory limitations still a problem?

Hum: Yes. The memory problem on testers has gotten much worse. The number of vectors generated these days is absolutely enormous. There are two things to worry about: One is the amount of memory you have on a tester, and the other is test time.

While memory is pretty cheap these days, the problem with putting more memory on testers is that you then have to clock all the test vectors into your part, and on scan chains you generally limit the clock speed because of power problems, increasing test times drastically. So, TestKompress's ability to compress test vectors and reduce test time is very important.

T&MW: What is driving interest in design for yield (DFY)?

Hum: Yield learning is taking a lot longer than it did. Folks typically use test chips to determine basic transistor characteristics and to calibrate Spice models. Library vendors then build models that run on simulators and timing analyzers, and people construct various geometries to calibrate their OPC [optical proximity correction] processes and, when that's done, say this node is now ready for production. But they do their first couple of masks and get their first chips through and find yield isn't what they expected. They scratch their heads and ask what happened. DFY can prevent these kinds of problems.

T&MW: What is the next level in DFT?

Hum: The next level is going to be its application to this yield enhancement. If you have made an investment in scan design, you will be able to use your investment to analyze, control, and improve yield. We believe the next level of DFT is going to be the addition of diagnostics so you'll be able to diagnose thousands of parts rather than tens of parts per design, as you do today.

T&MW: Have test-bench languages like e and Vera had a positive effect on errors?

Hum: With any new technology, you need to ask what value it adds. A technology can make you more productive while not fundamentally changing what you are doing, or it can represent a shift in methodology that improves productivity and solves a problem. My research shows that the use of test-bench languages such as Vera and e has had a productivity impact but no discernible impact on the number of errors per design. If you had two spins per design before buying into Vera or e, you will still have two spins per design afterward.