2005 efforts suggest 2006 ATE and DFT trends
Rick Nelson, Chief Editor -- Test & Measurement World, 2/1/2006
The semiconductor ATE industry will spend 2006 adjusting to the product innovations and organizational changes that were initiated in 2005. EDA vendors are working to speed test generation, enhance diagnostics, improve fault coverage, and derive yield-enhancement data from the results of scan-based test.
For SOC test, Advantest has claimed success with its T2000 OpenStar system, despite the lack of participation of other SOC ATE vendors in the OpenStar program. (RFIC tester maker Roos Instruments does participate.) My colleague Jeff Chappell at Electronic News (Ref. 1) reports that the T2000 achieved 36% market share in the first half of last year.
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| Fusion EX is one of several configurations that let customers tailor the Fusion architecture to their needs. Courtesy of LTX. |
Agilent, whose semiconductor test operation will emerge as Verigy after a mid-2006 spin-off and IPO, introduced last year its InstaPin per-pin licenses for 93000 Pin Scale digital cards, which let customers cost-effectively allocate test capability. For its part, LTX last year debuted 40-slot MX and 80-slot EX systems to complement its 20-slot Fusion CX system.
As Agilent and LTX continue evolving 93K and Fusion, Credence Systems is consolidating its Sapphire technology, acquired with the 2004 NPTest acquisition, into its product portfolio, phasing out its Octet and Quartet platforms. The Sapphire line-up now includes the NPTest-derived Sapphire S platform as well as the Sapphire D-10, a low-cost system introduced in July that offers CompactPCI compatibility.
In addition, Teradyne is expanding its FLEX lineup, now available in microFLEX and ultraFLEX configurations, and the company recently worked with Cadence Design Systems to ensure smooth interfaces between FLEX platforms and Cadence Encounter Test tools (see box below).
In other EDA activity, Synopsys has recently enhanced TetraMAX to speed up ATPG runtime performance and to add a new waveform debugger that helps designers quickly isolate and correct design-for-test problems.
Mentor Graphics introduced its YieldAssist diagnostic tool, which allows semiconductor manufacturers to harvest device failure information from wafer sort to adaptively improve manufacturing-test quality.
A key goal of getting ATE systems to work well with EDA tools like Encounter Test, TetraMAX, and YieldAssist is "getting more out of test"—that's the theme of the 2006 International Test Conference, which is scheduled to commence October 22 in Santa Clara and which will provide the ideal time to see how well ATE and EDA vendors have built on their 2005 momentum.
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Teradyne FLEX platforms running IG-XL software now support Cadence Design Systems Encounter True-Time Delay Test patterns in industry-standard STIL or WGL format and Encounter Diagnostics Chip Pad Pattern (CPP) format, establishing a validated flow for test and yield diagnostic information between FLEX systems and Encounter Test software. Teradyne and Cadence also validated a path from Teradyne ATE to Encounter Diagnostics to help customers resolve ATE failures and enhance their yields. 
