Material changes
Steve Scheiber, Contributing Technical Editor -- Test & Measurement World, 3/1/2006
In its biannual International Technology Roadmap for Semiconductors (ITRS), the Semiconductor Industry Association offers some bold predictions (Ref. 1). Although the document aims primarily at device-level manufacturing and test, its conclusions suggest considerable challenges at the board and system levels as well.
The ITRS predicts more aggressive scaling than it has in the past. Feature dimensions reached 90 nm in 2004, less than the 100 nm predicted for 2005 in 2001. Current expectations are for 25-nm transistor gates to arrive in 2007—six years earlier than forecasted in 1999. According to the Roadmap, by the end of the decade, memory will cost an eighth of what it does today, and microprocessor speeds will have tripled.
As features continue to shrink and devices combine numerous functions and technologies on a single piece of silicon, devices will feature either huge numbers of I/O pins or else fewer pins with the chip generating large amounts of logic and processing before sending signals out. The increasing circuit complexity will complicate test and inspection tasks at board and system levels as well. Developing comprehensive functional tests at the board level, for example, will require taking advantage of test capabilities that designers must include on the devices themselves to make them manufacturable.
Many of these technological innovations will appear first in consumer products, where enormous demand and severe price pressures will challenge manufacturers to tightly control production processes and create efficient, cost-effective test and inspection strategies at least as well as they do today. According to the Roadmap, "some of the most important test challenges are actually centered on some of the more subtle historical missions of manufacturing test—reliability and yield learning."
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| The GaAs MOSFET breakthrough was enabled by unpinning the Fermi level at the oxide-GaAs interface using a Ga2O3 template layer and a GdGaO dielectric layer. Courtesy Freescale Semiconductor. |
The SIA Roadmap's stated purpose is to "guide shared research by industry, universities, and national labs," particularly calling attention to areas that no known manufacturing solution can support. "It is in these areas that breakthroughs in research are needed."
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Test and inspection took center stage at APEX (February 8–10, Anaheim, CA; IPC, 
