DRAM test: At the crossroads?
Rick Nelson, Chief Editor -- Test & Measurement World, 4/1/2006
DRAM technology has reached a juncture requiring significant revisions in test approaches—unless, of course, it hasn't. ATE powerhouses Advantest and Agilent Technologies have staked out significantly different positions on what emerging DRAM technologies will require.
Debbora Ahlgren, an Agilent Automated Test Group VP & GM, believes that XDR (extreme data rate) and GDDR (graphics double data rate) DRAMs will require new test approaches to ensure high quality at low cost of test (Ref. 1). She cited the type of faults appearing in memories fabricated in 65- and even 45-nm processes as one reason for the new test requirements. Such devices are subject to random defects, including delay defects that, she said, require an at-speed tester-per-pin architecture to be reliably detected.
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| The T5501 is well positioned to test devices through GDDR4, according to Gary Fleeman, director of product engineering. Courtesy of Advantest. |
In contrast, Gary Fleeman, director of product engineering at Advantest, doesn't foresee any near-term challenges that will be insurmountable to the installed base of memory testers, including his firm's T5501, which targets multisite test of DDR and GDDR devices. He said the T5501, which operates at 2.133 GHz in DDR mode, is well positioned for DDR3 devices as well as for GDDR4.
He did note that the ever-increasing I/O speeds of graphics memory will ultimately challenge the installed base, and he suggested that his firm's 6.5-Gbps digital module, which initially targeted Serdes test (Ref. 2), will play a role in at-speed test of memory interfaces. In fact, in highlighting the module at Semicon Japan in December, Advantest specifically cited its applicability to DDR and XDR DRAM test.
The Advantest 6.5-Gbps module plugs into the company's T2000 SOC tester. But Fleeman doesn't see the T2000 evolving into a single-insertion memory-test platform. In fact, he said, "I don't see anybody's 6.5-GHz pin electronics becoming part of single-
insertion memory test approach. It is absolutely the case that all mainstream memory test today is dual insertion, and emerging new parts are not going to be core tested at I/O speed. The industry has clearly settled on a structural core-test insertion with long test times and then an at-speed I/O test. We've already started down that road, and we are not looking back."
I'll look back in a few months to see which memory-test roads are well traveled.
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