Know your test hardware
An exclusive interview with a test engineer
Staff -- Test & Measurement World, 4/1/2006
John Slezia is a test engineer and a member of the technical staff at Cypress Semiconductor's manufacturing test group in Bloomington, MN. Cypress produces synchronous and asynchronous memories, first-in/first-out (FIFO) memories, and USB interface devices on 8-in. wafers. Slezia has held several positions in several locations since joining Cypress in 1983. He is employee number 44. Martin Rowe spoke with him on the phone.
Q: What are your responsibilities in the manufacturing test group?
A: My duties include monitoring the test floor for yield. I'm also responsible for test programming and test-time reduction on 100 test cells. Each cell contains an automatic digital IC tester. Most of the test cells contain purchased systems, but some were developed in-house. These test cells typically support as many as 50 devices on the floor at any time.
Q: What is the test process for testing devices while still on a wafer?
A: Wafers make three test passes, called sorts. In the first sort, we test parts with their temperature at 88°C and sort them into three categories: prime, repairable, and failed. We create an electronic map of the wafer that identifies failed and repairable devices—we don't drop ink on failed devices anymore.
We then use lasers to repair the devices and retest all prime and repaired parts at 88°C in the second sort. Those parts that pass the second sort get tested again at –40°C. These last two tests guarantee compliance to the Cypress Data Sheet.
Q: How long does it take to test all the devices on a wafer at each pass?
A: That depends on the device size and circuit complexity. Some wafers have as many as 20,000 parts while others have 200. Test time ranges from less than 1 s to 40 s per device. Average sort time is now 135 min per wafer. It used to be 221 min per wafer. A particular wafer that used to take 92 min to test now takes 18 min.
Q: How did you reduce test time so drastically?
A: I optimized the test programs to make them more efficient. I didn't remove any tests, but I did rearrange them to better utilize my test equipment and significantly reduce the cycle time of the tester. I did that because I have an intimate knowledge of how the test systems work. I identified a sensitivity in the tester's hardware that the manufacturer had to repair. As a result of the reduced test time, we were able to test more wafers in Bloomington instead of testing in Asia where we cut and package the wafers.
Q: What other changes have you made to make testing more efficient?
A: We monitor the test process in real time rather than test a batch of wafers and then analyze the data. We immediately analyze the data for every wafer, looking at 15 parameters. Because we test the devices in blocks of eight or 16 test sites, we can tell if a set of wafer probes is bad by analyzing what we call "site deltas." That is, we compare the data at the same relative site in each block. If the device in the same site in each block fails, we stop testing and fix the problem.
We analyze this data at the end of every wafer test using remote computers connected to the test on the company LAN. We then download the analysis to the tester while the next wafer is under test. If we find a problem, we stop the process, fix the problem, and retest the wafer in question. In the past, we would have tested 25 wafers before finding that the same site experienced a continuity problem. Now, we retest no more than one wafer. Some wafers may take hours to test, and we don't want to retest 25 wafers.
