A semiconductor test primer

VLSI Test Principles and Architectures: Design for Testability, Laung-Terng Wang, Chen-Wen Wu, and Xiaoquing Wen (editors), Elsevier Science (www.books.elsevier.com), 2006. 706 pages (prepublication review copy). $49.95.

Representatives of Cisco Systems, Cadence Design Systems, Wavecrest, Intel, LogicVision, Mentor Graphics, and SynTest represent EDA toolmakers and semiconductor designers and manufacturers, yet they refrain from giving the hard sell on any particular products. One of the few sections to mention specific EDA products is a chapter on test compression, and the editors provide a balanced look at multiple vendors' offerings. A section on RAM BIST compilers notes that commercial implementations are available, but it confines its description to an academic version. The book, expected to ship June 30, will come with a CD containing SynTest software.

Chapter 1 defines some basic test terms. You can skip this section, but if you're unclear on the distinction between fault and failure, for instance, you may want to give it a look. To demonstrate that the authors aren't restricting their efforts to chip test, the opening chapter introduces board test and boundary-scan technology as well.

Chapter 2 delves into design-for-testability, covering controllability and observability and various types of scan cells. Chapters 3, 4, and 5 build on this information, covering logic and fault simulation, test generation, and BIST. Chapter 6 introduces test compression and includes comments on five vendors' products. Chapter 7 rounds out the broad discussion of testability by covering logic diagnosis and its application to design debug, failure analysis, and yield ramp-up.

You can choose among subsequent chapters based on your area of interest. Chapters 8 and 9 address memory test and repair. Chapter 10 goes into detail on boundary-scan and core-based testing, covering the IEEE 1149 dot-4 and dot-6 extensions for AC-interconnect and analog test as well as the IEEE 1500 standard for SOC core test. Chapter 11 covers analog and mixed-signal test. The concluding chapter looks at the emerging problems facing scan and BIST as process geometries shrink below 65 nm.

Much of the information here could be gleaned from industry white papers and from perusing years and years of ITC and VLSI Test Symposium proceedings, but this book is a valuable collection of relevant material in a convenient package.