Limits of test time reduction
Calculating the optimal compression level will provide the highest return on silicon resources.
By Chris Allsup, Synopsys -- Test & Measurement World, 6/1/2006
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Nanometer fabrication processes offer higher circuit density and better performance but also present new challenges. Systematic and random defects that were a nuisance above 90 nm are now killer defects. To maintain quality, more test patterns must target larger numbers and more types of defects. And as circuit density increases, the number of internal scan elements, and hence the length of scan chains, increases. More scan patterns and longer scan chains can inflate test-execution time by a factor approaching the square of the die area, and SOC test costs increase by the same factor.
On-chip scan compression technology has emerged as a way to reduce test- execution costs by reducing the time spent testing digital circuits (Ref. 1). Various scan-compression architectures are available, all of which reduce test time by creating x times more scan chains with approximately x times fewer scan elements in each scan chain. Compression effectively reduces the time it takes to scan each test pattern. For a scan-compression factor of x (assuming the scan chains are well balanced with no pattern inflation issues), test application time reduction is:
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Note that TATR is an asymptotic function. For example, a 20-times scan compression (x = 20) reduces test application time by 95% (TATR = 95%), whereas a 50-times compression achieves 98% TATR. 100-times compression reduces test application time by 99%, an improvement of only 1% compared with 50-times compression.
By using a cost model, you can determine whether there are benefits in targeting more than about 20-times scan compression. Some researchers (Ref. 2) have expanded upon a DFT cost model (Ref. 3) to compare different scan-compression methods, but you need an additional model to determine the optimal amount of compression.
I have developed a framework for evaluating the full economic impact of implementing scan compression. Using this model, you can determine whether additional compression offers any benefits and, if so, what the actual cost savings are. Moreover, I have developed equations that let you compare compression implementations in terms of their impact on silicon area so you can evaluate which approach is the most cost effective.
Test execution and silicon areaCompanies most likely to value large reductions in test application time are thosewith very high manufacturing volumes where even a penny saved per die could add up to millions of dollars over the lifetime of a product. Under these conditions, very high TATR is desirable despite the fact that, as is evident from equation 1, the cost savings in percentage terms diminishes beyond 20-times compression.
The decision to add more compression, assuming it is easy to implement, comes down to a tradeoff between two costs: test-execution cost, Cexec, and silicon area overhead cost, Csilicon. Increasing the amount of compression to reduce test application time will continue to provide cost savings as long as the sum of test-execution cost and silicon area overhead cost continues to decline. You should therefore increase compression from a nominal level x to an optimal level λ that minimizes total cost, where Ctotal = Cexec + Csilicon (Figure 1).
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| Figure 1. Cost of test calculations must take into account silicon area overhead costs and test-execution costs. Minimum total cost of test here occurs at λ. |
If you assume that tester utilization is high (greater than 90%) so that test-execution time for digital circuit testing is a bottleneck, and that non-tester hardware costs for test are much less than tester hardware costs, then test-execution cost as a function of compression level x is:
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and the silicon area overhead cost per die is:
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From equations 2 and 3, the total cost is:
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In these equations, Ract is the cost of active testers ($/s); Ttest is the test-execution time (s); Tsetup is the setup time for an IC on the tester; Kt_time is a constant relating test time to die area (s/cm2); and α(x) is a scalar that takes into consideration the fact that failing die require less test time:
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where βfail is the percentage of good-die test time required on average to test a defective die. A(x) is die area at compression level x. The amount of compression circuitry increases as the number of scan chains is increased, so A(x) can be represented as a linear function of compression:
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where A0 is the area of the die without any compression, and γ is a scan compression area scaling factor representing the fractional area increase in die size per unit increase in compression. Cs is a silicon area cost multiplier ($/cm2). Y(x) is the yield at compression level x and depends on the defect density D (defects/cm2):
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The cost saving gained by increasing compression from x to the optimal level γ corresponding to where the total cost Ctotal reaches its minimum is:
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Figure 2 illustrates cost savings for various die areas A0 after substituting equations 5–7 into equation 4 and then applying equation 8. The input parameters used for this example are typical of current manufacturing environments. For each compression level x, the cost saving for a particular curve corresponds to savings that would be incurred by increasing the level of compression from x to λ. (In Figure 2, values of λ are very close to the compression numbers corresponding to the lowest portion of the curves, intersecting the $10 cost saving grid line.) For example, for the curve A0=1.0 cm2, the cost saving gained by increasing compression from x=10 to λ=46 is just under $100,000 per 1 million units.
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| Figure 2. Cost savings are shown per 1 million units for different die areas, A0. Here, D=0.3 cm–2, Kt_time=20 s/cm2, Ract=$0.06/s, Cs=$4.00/cm2, ßfail=50%, and γ=10–4. |
All designs benefit from compression, but because test-execution time is proportional to the square of the die size, the largest designs benefit the most in dollar savings. At any compression level less than the optimal compression level, there is more time left over to "squeeze" incremental savings by applying further compression.
Cost difference of compression schemesYou can evaluate the difference in test costs between two scan compression implementations, SC1 and SC2, assuming the same design effort but different silicon area overheads for the same level of compression. All other factors being equal, the solution with the lowest area overhead across compression levels will be the most cost effective. Using equation 6, the areas are:
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where the ratio γ2/γ1 represents the comparative area overhead between SC1 and SC2.
Consider the case in which SC2 has a higher scan compression area scaling factor than SC1: γ2>γ1. The higher area scaling factor γ2 means the optimal compression level for SC2 (λ2) is less than that for SC1 (λ1). Comparing the total cost difference between the two implementations at compression levels x<λ2 underestimates the cost difference that is attainable when both are implemented at their optimal levels. Conversely, cost comparisons at x > λ1 overestimate the difference. The total cost difference, Δcost, should instead reflect the difference between the two cost minima:
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Substituting the relations in equation 9 into equation 4 and then using equation 10 for the cost comparisons, observe from Figure 3 that total cost difference due to an increase in the comparative area overhead γ2/γ1 increases rapidly in proportion to die size.
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| Figure 3. Cost difference per 1 million units are shown here as a function of γ2/γ1 for different die areas A0. Here, D=0.3 cm–2, Kt_time=20 s/cm2, Ract=$0.06/s, Cs=$4.00/cm2, ßfail=50%, and γ=10–4. |
You can derive simple formulas to evaluate the cost savings from compression, the optimal compression level λ for a design, and the cost difference between scan compression implementations. First, Tsetup does not influence compression tradeoff and can be ignored for comparative analysis. Second, the scan compression area scaling factor γ is small (on the order of 10–4), so if you expand the expression for A(x) in the equation that defines Ttest for equation 2, you find the contribution of compression logic to test-execution time is negligible. This is reasonable from the perspective that the compression logic can be tested very quickly compared to the rest of the chip.
As a result, the expression for A(x) in equation 2 can be approximated by A0 without much loss in accuracy. Furthermore, you may simply replace the product term Kt_timeA0 2 with T0, the test-execution time in seconds that would be in effect for a design without the use of scan compression. Assuming the scan chains are well balanced:
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In addition, Y(x) in equation 2 can be approximated by Y0 because the increase in test execution cost due to the very small decrease in yield caused by adding compression circuits is negligible compared to the cost saving. Finally, note that the scalar that accounts for less time spent testing failing die has very little dependence on the amount of compression, so α(x) can be approximated by α0. With these simplifications in mind, equation 4 reduces to:
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The cost saving gained by implementing compression level x is the difference between test-execution cost without compression and total cost with compression:
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Substituting the linear expressions for compression area (equation 6) and yield (equation 7) into equation 13 gives:
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The total cost reaches a minimum where the derivative of equation 14 is zero:
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Substituting equations 6 and 7 into equation 12 and solving equation 15 for x yields this formula for the optimal compression level λ:
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The derived formula values are accurate to within ±1.2%, standard deviation = 0.6%, compared with the entire data set of λ measured from equation 4.
You can also derive a closed expression for the cost difference between compression solutions that can be used to evaluate the cost effectiveness of alternative compression implementations. The comparison can be made by substituting the simplified form of Ctotal (from equation 12) into equation 10 and then using the derived formula of λ in equation 16 to find the cost difference. Δcost reduces to:
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Figure 4 displays total cost difference Δcost just as in Figure 3, except it focuses on three initial die areas to compare the derived estimates for Δcost in equation 17 with those obtained using the full calculation.
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| Figure 4. Cost difference per 1 million units as a function of γ2/γ1 for different die areas A0 illustrate the accuracy of derived formulas vs. full calculation. Here, D=0.3 cm–2, Kt_time=20 s/cm2, Ract=$0.06/s, Cs=$4.00/cm2, ßfail=50%, and γ=10–4. |
Scan compression greatly reduces test-execution costs, but the silicon area overhead cost of compression limits how much test application time reduction is cost effective. For any design, there is an optimal compression level proportional to the square root of the die size that provides the highest return on silicon resources. This optimal level is sensitive to the area overhead of compression and other architectural aspects.
AcknowledgementsThe author would like to thank Rohit Kapur, Synopsys scientist, and Tim Ayres, Synopsys principal engineer, for their valuable suggestions on ways to improve this manuscript.
| Author Information |
| Chris Allsup, marketing manager of test automation products at Synopsys, has more than 20 years combined experience in IC design, field applications, sales, and marketing. He earned a BSEE degree from U.C. San Diego and an MBA degree from Santa Clara University. |
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