Global TMW:
Login  |  Register          Free Newsletter Subscription
Subscribe
Email
Print
Reprint
Learn RSS

Boundary scan accelerates VoIP test

Karla May, Manager of Strategic Accounts, Corelis -- Test & Measurement World, 8/1/2006

As more new processors and communication electronics are designed to include boundary-scan chains, boundary-scan testing of multiple circuit boards in parallel is becoming a way to cut both time and costs out of the test cycles of product manufacturing. A single operator can test multiple boards simultaneously from a single PC. With these new boundary-scan (JTAG) tools, it takes the same amount of time to test four boards as 1000.

A simple test setup involves connecting the test controller to a PC through a PCI, USB, LAN, or cPCI interface, then to multiport TAP pods to accommodate the UUT.

Zultys Technologies, a maker of VoIP products, is embracing boundary scan as the company acts to take advantage of enterprise-level VoIP applications that are predicted to grow at 20% annual rates through 2009. To meet its time-to-market, costs, and quality requirements, Zultys is employing Corelis boundary-scan hardware to perform concurrent testing and programming of multiple units without operator intervention. With the Zultys implementation, Test Access Ports (TAPs) on a remote test pod have a dedicated pin on the JTAG interface connector that can detect the presence of the target board. The software monitors the state of this signal to detect both the presence of the target device as well as the proper insertion of the test cable.

The hardware applies simultaneous test vectors and in-system programming (ISP) patterns to each board, and it performs individual, simultaneous verification. Any failure of one board will be logged but doesn't prohibit the continuation of testing on all the other units under test (UUTs). From there, additional hardware choices fan the connection out to accommodate more and more units at once.

The details of how Zultys applies boundary scan in its "push-line" conveyer-belt assembly process are available in a paper at www.corelis.com/products/WhitePapers.htm#zultys.

Email
Print
Reprint
Learn RSS

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

Related Content

 

By This Author

There are no other articles written by this author.

Sponsored Links



 
Advertisement
SPONSORED LINKS

More Content

  • Blogs
  • Podcasts

Blogs

  • Martin Rowe
    Rowe's and Columns

    July 8, 2008
    Introducing...Test ideas
    Beginning in the T&MW August print issue, we’ll replace the “Project Profile” ...
    More
  • Rick Nelson
    TAKING THE MEASURE

    July 1, 2008
    S-parameters are so yesterday
    Textbook amplifiers operate in linear mode and are easy to analyze. Unfortunately, it’s often ...
    More
  • » VIEW ALL BLOGS RSS

Podcasts

Advertisements





NEWSLETTERS

Click on a title below to learn more.

Test Industry News (3 Times Per Month)
Machine-Vision & Inspection (Monthly)
Communications Test (Monthly)
Design, Test & Yield (Monthly)
Automotive, Aerospace & Defense (Monthly)
Instrumentation (Monthly)
Resource Center E-Alert (Monthly)
©2008 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy
Please visit these other Reed Business sites