PCI Express: Beyond minimum compliance

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You should note, however, that this software was designed to provide a "snapshot" of minimum compliance and was never designed to be a complete compliance tool for PCI Express. The SIG software measures and reports on just four parameters (V_TXA, V_{TXA_d}, T_TXA, T_{TXA-MEDIAN-to-MAX-JITTER}), while the specification for full compliance requires manufacturers to measure and report on a total of 30 parameters, in accordance with the PCI Express, Revision 1.1 Base Specification and Card Electromechanical Specification (Refs. 1 and 2). Tables 1 and 2 show differential transmitter output specifications and differential receiver input specifications, respectively. In addition, reference clock peak-to-peak phase jitter must not exceed 86 ps for a 10^–6 BER or 108 ps for a 10^–12 BER. (See "REFCLK phase jitter specifications").

The PCI SIG software is useful for customer demonstrations, but more-robust commercial compliance-test packages, which are available from a variety of vendors, address the comprehensive list of parameters called out by the PCI Express specifications. You can take advantage of these commercial packages to create products that are not just compliant, but that have higher design margins and improved production yields.

When evaluating commercial packages, you should compare their capabilities with respect to the PCI Express specifications to find the package that performs the tests you need. You should also take the time to understand the methods each package uses for the underlying measurements, as these measurements are used to derive other results during parametric (jitter, noise, and BER, also termed JNB) testing.

Figure 1.  The top right eye diagram indicates degraded performance relative to that depicted in the top left diagram. The corresponding histograms suggest the lack of a PCI Express-compliant clock.

Using the right compliance tools is not a "nice to have" capability but a matter of maintaining competitiveness in the marketplace. Passing parts that have limited design margins can cause serious business issues. While such parts may pass the minimum compliance tests, if they later fail in the field, they will affect the bottom-line profits of a product line or business unit.

Figure 2.  An eye mask (top) enables go/no-go testing, while a histogram (middle) indicates the jitter of rising and falling data edges relative to the clock signal. The bathtub curve data enables derivation of DJ, RJ, and TJ values using a tail-fit algorithm.

Robust packages provide diagnostic tools for both clock and data. Without first verifying the clock signal is accurate, you are at risk for propagating relatively small errors into very large errors.

Here are some examples of detailed views used for diagnostics. Figure 1 shows the test results of a PCI Express data signal with and without using a compliant clock. Figure 2 shows an eye diagram, a jitter histogram, and bathtub measurements on a PRBS 2²³–1 pattern. The Wavecrest TailFit algorithm (Refs. 3 and 4) applied to the jitter histogram yields RJ, DJ, and TJ results in about 1 s, measuring a signal from a pattern generator.

Other functions that can help evaluate PCI Express compliance include marker tools that can indicate jitter characteristics in several formats, including fast Fourier transforms (FFTs). In addition, clock/PLL tools can help isolate the cause of a Serdes problem that stems from a faulty reference clock or PLL. Click here to see graphical examples of marker and clock/PLL tools and illustrates, for example, how you can use FFT and 1-sigma vs. span views to identify sources of jitter such as crosstalk or power-supply noise in order to find and eliminate problems.

Figure 3.  These images show the test results for a transmitter’s signal/jitter output and associated TJ at BER = 10–12: (a) full-swing eye, (b) de-emphasis eye, and (c) BER CDF bathtub curve.

In this figure, the measured eye-opening is 0.694 UI (or TJ = 61.2 ps). The minimum specification for the transmitter eye opening is 0.75 UI; therefore, this PCI transmitter marginally fails the compliance test.

Figure 4 shows the data-dependent jitter (DDJ) distribution, PJ, and RJ power-spectrum density (PSD) for the same transmitter. Transmitter jitter output diagnostics test results measure DDJ as a function of the UI span. The DDJ histograms are reviewed for rising (green) and falling (purple) edges, respectively. The lower left diagram depicts a "zoom in" for the worst-case DDJ locations. The lower right diagram shows both PJ and RJ PSD shape.

Figure 4.  Shown here are data-dependent jitter (DDJ) distribution and PJ and RJ power-spectrum density (PSD) for the transmitter that failed the compliance test in Figure 3. The DDJ histograms are reviewed for rising (green) and falling (purple) edges, respectively. The lower left diagram depicts a “zoom in” for the worst-case DDJ locations, and the lower right graph shows both PJ and RJ PSD.

Once you choose a software package for your PCI Express compliance tests, you should use the same instruments and test methodology throughout the entire product cycle. This will permit a seamless transition from development to design characterization to high-volume production, which will save time, reduce test costs, and improve time-to-market for your company. Using a single methodology in all cases will eliminate the confusion that could arise from measured values that were generated by different methods and platforms.

The authors would like to thank Dennis Petrich of Wavecrest for his assistance.