DFM, DFY get EDA industry emphasis

Design for manufacturing (DFM) and design for yield (DFY) are becoming increasingly hot topics as EDA companies attempt to help chip makers contend with random defects and process variations that can prevent fast, profitable ramp to volume in 65-nm and below process technologies. Tools addressing DFM and DFY issues are available from the big EDA firms, including Cadence, Magma Design Automation, Synopsys, and Mentor Graphics. Such tools provide optical proximity correction (OPC) and support resolution (or reticle) enhancement technology (RET), they provide critical area analysis (CAA) and address the effects of chemical mechanical polishing (CMP), they enable manufacturing-aware design rule checking (DRC), and they can perform parametric yield measurement and optimization. Beyond those functions, Cadence’s Precision Router lets designers model manufacturing effects during the design process.

DFM and DFY tools overcome the one-way barrier between design and production; they make use of or assist in the capture of manufacturing data for use in the design process.

John Lee, GM of the physical verification business unit at Magma Design Automation, noted that integration extends to foundries’ reference flows, pointing out as an example that Magma tools have been qualified by IC-manufacturer TSMC.

Conversely, point-tool makers emphasize a laser-like focus on a particular DFM/DFY niche: “Our motivation in starting Stratosphere Solutions was to build differentiated technology that meets a focused market demand,” said Prashant Maniar, chief strategy officer of the firm, which develops silicon intellectual property (IP) designed to help silicon manufacturers reach DFM and DFY goals through process-variability characterization.

What DFM and DFY tools generally have in common is the ability to make use of actual manufacturing data in the design process or to assist in the capture of such data. OPC, CMP, and CAA tools generally work with test-chip data, which can be captured with the aid of Stratosphere’s StratoPro, for example. Tools like Mentor Graphics’ YieldAssist moves beyond the test-chip level to continually obtain yield-enhancement data from production-test systems.

Some DFM/DFY tools don’t attempt to alter a design to comply with manufacturing requirements—they just give you a more accurate picture of how your design will translate to real silicon. Steve Smith, senior director of marketing for the Synopsys Galaxy platform, cited an example: For one chip, a worst-case-corner analysis indicated a customer could guarantee only 404-MHz performance, whereas the Synopsys PrimeTime VX variation-aware statistical static timing analyzer (SSTA) showed a 99% probability that the chip would run at 474 MHz.

For more on DFM/DFY tools and suppliers, click here.