Test Compression

In scan-test mode, scan structures allow each sequential gate to be concatenated with other sequential gates and configured as a long shift register called a scan chain. Each sequential gate can be loaded with a predefined value and treated as a control point.

Once the device captures values into the sequential elements, an automated tester can enable scan test and “observe” results. Instead of trying to create patterns for a complex sequential circuit, all sequential gates behave as control and observe points. Overall, the test problem is reduced to testing the small blocks of combinational logic between the sequential gates. Scan simplifies the test problem enough that automated test pattern generation (ATPG) tools can quickly and efficiently create test patterns.

Historically, as devices grew in gate count, scan test data volume and application time grew as well. A device that contains twice as many gates as the previous generation has scan chains that are twice as long, unless more scan chains are added. This is due not only to larger designs but also to the additional pattern types necessary to detect newer defect mechanisms. At the same time, these larger designs are moving to more modular and hierarchical design methodologies, creating the demand for fewer test signals from each circuit block.

As a result of the emergence of new fabrication technologies, standard stuck-at scan tests are no longer sufficient. Many companies have seen significant growth in the number of timing-related defects at 130 nm and below. At-speed scan testing has become necessary to detect this growing population of defects, but unfortunately, the most popular approach for at-speed scan requires a more complex pattern.

The most desirable application of at-speed scan test involves loading values into the scan chains at a slow clock rate and then applying two cycles at the system clock frequency. At-speed patterns can use internal PLLs for the at-speed launch and to capture pulses to provide accurate clocking. Because two cycles are required in the functional mode of these tests, at-speed scan patterns are typically three to five times larger than a stuck-at pattern set. Note that ATPG tools can support at-speed scan tests that are simpler and require fewer patterns—these are called launch-off-shift patterns. Such tools impose more design constraints, however, and will test more nonfunctional logic, possibly reducing yield.

Figure 1. New tests related to timing are needed to cover new defects introduced by fab process changes.

In addition to using at-speed scan testing, some companies are starting to apply tests that target specific types of defects or the physical locations where certain defects are most likely to occur. One new pattern type statistically targets bridge defects that may have escaped stuck-at pattern tests. The idea is to detect a fault at each gate terminal multiple times while randomly changing how the fault is detected. This pattern type is referred to as multiple-detect pattern and can be created for stuck-at and transition faults.

Another new family of tests is based on targeting physical locations within the device layout database (GDSII) to identify the most likely defect locations. Since these tests use design-for-manufacturing (DFM) layout rules to identify the likely defect locations, they are often called DFM-based fault model tests. The first such fault model to be used is based on bridge extractions, and some manufacturers are using a combination of multiple-detect patterns and deterministic bridge extraction patterns (Figure 1).

As fabrication technologies evolve, test application time and test data volume are drastically increasing just to maintain test quality requirements (Figure 2). For example, new tests require:

Figure 2. The number of tests and corresponding data volume increase with each new fabrication process technology.

• greater than 2X the test time to handle devices that double in gate count but maintain the same number of scan channels,
• 3X to 5X the number of patterns to support at-speed scan testing for the growing population of timing defects at 130-nm and smaller fabrication processes, and
• 5X the number of patterns to handle multiple-detect and new DFM-based fault models.

This equates to a minimum of 10X compression for increased design sizes and at-speed test patterns just to maintain quality and tester throughput. If newer multiple-detect or DFM-based fault models are added, then the test time will increase to 20X.

Thus, the starting point is 10X compression just to maintain tester throughput and 20X if new fault models are used, which becomes 40X if the next design doubles in size. If you consider reducing the block-level routing and top-level scan pins by 5X, that means you need 5X more compression on top of the existing compression. Supporting multisite testing or DFM-based fault models will triple the compression requirements at a minimum. A major benefit of compression is to reduce test pin count, which is a major cost benefit at manufacturing. As a result, some companies are already looking for compression well beyond 100X tester cycle reduction.

A few important factors to consider with any compression technique are:

• the amount of compression possible,
• the scalability of compression (does the compression technique work with various design sizes, with few or many scan channels, and with different types of designs?),
• the robustness in the presence of X states (can the design maintain compression while handling X states without losing coverage?), and
• the ability to perform diagnostics of failures when applying compressed patterns.

Figure 3. The embedded-deterministic-test decompressor shown here employs a continuous-flow ring generator.

In Mentor Graphics’ EDT implementation (see Web-exclusive sidebar “Modular embedded deterministic test”), the initial ATPG process of determining which values to load into scan cells to detect as many faults as possible is exactly the same as in standard ATPG. This is true for any type of scan pattern. But if standard ATPG were used, it would use random values to fill up the unspecified scan cells that cannot improve targeted fault detection.

Instead, EDT processes the desired specified bits for the pattern and determines how to load them through the decompressor. When the resulting compressed pattern is loaded through the decompressor, the specified bits get loaded into their respective scan cells. A side effect of the decompressor is that all the unspecified bits get loaded with random data. As a result, lots of tester cycles are saved by not having to specifically load random data.

In a tester using EDT, scan-chain outputs feed into a compactor. Several scan chains are XOR-combined into individual scan channels. Each scan chain only propagates to one gate with this configuration, which controls routing congestion.

One of our most important considerations when developing the EDT architecture was how to handle X states. Even if no X’s are present in the design, the design may still need to accommodate X’s when considering false and multicycle paths for at-speed patterns. Other-wise, there could be huge losses in test coverage and compression.

Figure 4. An EDT compactor can mask unknown states from disrupting fault detection.

In EDT, many internal scan chains are loaded through a small interface of several scan channels. The ratio of internal scan chain to channels defines the maximum possible compression. EDT provides the following capabilities:

• very high levels of compression—many devices have been designed with effective compression in the 100X range;
• scalability—effective compression is possible with just one scan channel and has been used in smart cards that have only a three-pin test interface;
• compressed pattern diagnostics;
• no loss of coverage in the presence of X states, making possible the masking capability; and
• flexibility—the EDT logic is only based on the number of scan chains and works as a transform function (with no need to change the EDT logic due to core design changes as long as the number and interface to scan chains remains constant).

We found that the highest coverage using standard ATPG was reached by EDT for all six designs. Also, the EDT compression ratio (normalized for the coverage achievable by Illinois Scan) is noticeably better. As a result, a design configured with EDT compression logic can accommodate more patterns of various types within the same tester data volume and test application time. Even greater compression can be achieved by using the EDT compactor on the output that is capable of masking unknown states. Using a compaction technology without masking can result in huge coverage loss and lower compression.